KR100193448B1 - Package Burn-in Test Circuit of Semiconductor Memory - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a test circuit of a semiconductor memory, and more particularly, to a package burn-in test circuit of a semiconductor memory which reduces test time by enabling all word lines to be tested at the same time.

2. The technical problem to be solved by the invention

We want to solve the time delay that occurs during package testing.

3. Summary of Solution to Invention

A predetermined pin to which a predetermined stress voltage is applied, an enable signal generating circuit that is enabled in a predetermined mode in response to the stress voltage flowing into the pin, and a predetermined control in response to an output of the enable signal generating circuit A control signal generation circuit for outputting a signal, and charge supply means for outputting a predetermined test voltage in response to the output of the control signal generation circuit, and in response to the output of the control signal generation circuit; By implementing the package burn-in test circuit of the semiconductor memory device characterized by supplying a test voltage, it is possible to execute a high-speed test in the package state.

4. Important uses of the invention

A semiconductor memory device which performs a test operation at a high speed in a packaged state.

Description

Package Burn-in Test Circuit of Semiconductor Memory

1 is a diagram illustrating a power supply voltage application for a package burn-in test according to an embodiment of the present invention.

2 is a circuit diagram of a voltage level detector for detecting a voltage applied to an external pin as applied to the present invention.

3 is a detailed circuit diagram of an enable signal generation circuit for a package test.

4 is a circuit diagram related to a circuit for generating control signals applied to FIG.

5 is an operation timing diagram of various signals shown in FIGS.

The present invention relates to a test circuit of a semiconductor memory, and more particularly, to a package burn-in test circuit of a semiconductor memory which reduces test time by enabling all word lines to be tested at the same time.

Various tests are performed to increase the reliability of the semiconductor memory device. Representative test methods include wafer burn-in test and package burn-in test. Literally, the wafer burn-in test (hereinafter referred to as the WBI test) is to apply a high voltage to the chip in the wafer state to remove the defective parts early, and the package burn-in test (hereinafter referred to as the PBI test) is a chip in the package state. It means to remove the defective part early by applying high voltage. The removed portion is replaced by using a redundancy device that is essentially mounted in the current memory device. As described above, most semiconductor memories have undergone a burn-in test in a package state for several hours or more. Such a test is indispensably performed to indicate the reliability of the semiconductor memory device by guaranteeing the user the life of the completed memory device.

After these tests, the memory device is shipped to the user. The defect mainly found in the PBI test is a defect in the memory cell array. The reason why many defects are found in the memory cell array as described above is as follows. That is, an access transistor constituting a conventional DRAM unit memory cell is composed of an NMOS transistor, and a high voltage is applied to a gate signal, that is, a word line voltage, that controls the access transistor during an access operation. . Due to stress caused by the strong electric field generated by the word line voltage of the high voltage level, the gate oxide of the access transistor is likely to be destroyed. The destruction of the gate oxide film generated through such a process is most of the defects in the semiconductor memory device. In this case, the memory device cannot perform normal operation. Of course, defects are also found in a number of peripheral circuits, or core parts such as sense amplifiers and equalization circuits, but this is only a small amount compared to the defects in the memory cell array.

As the degree of integration of semiconductor memory increases, the time due to the PBI test becomes longer, and thus, a huge impact on productivity is exerted due to an increase in test cost. Therefore, various efforts have been made to improve the productivity by reducing the test time. Recently, the WBI test, which enables all word lines to be tested at the same time in a wafer state, has been executed, which is described in detail in Wafer Burn-in Technology for RAM's in the paper IEDM submitted by Toshiba, Japan.

In this paper, the voltage required to enable the word line during the WBI test is applied from the outside through a monitor pad built in the memory device, and applied through the monitor pad according to the stress applied to the word line. The voltage level can be changed. Currently, applying these WBI test methods to PBI tests results in faster tests, but not immediately. The reason is that in the package state, since the monitor pad does not protrude outside, the voltage required to enable all word lines cannot be supplied externally.

Accordingly, an object of the present invention is to provide a package burn-in test circuit of a semiconductor memory device which performs a test at a high speed by simultaneously enabling all word lines using a power supply voltage.

Another object of the present invention is to provide a package burn-in test circuit of a semiconductor memory device having improved productivity through high speed testing.

In order to achieve the objects of the present invention, the package burn-in test circuit of the semiconductor memory device according to the present invention, by detecting a plurality of pins for receiving a predetermined level of voltage in the package state, and the voltage applied to the plurality of pins An enable signal for generating enable signals for package test by combining a voltage level detector for generating test clock signals in a predetermined mode, and signals generated by internal circuits in the mode with the test clock signals. Receiving power through the power supply unit 50 consisting of a generation circuit, a diode and a control switch and receiving the enable signals of the enable signal generation circuit to generate a predetermined test voltage and simultaneously apply it to a plurality of word lines. Characterized in that the charge supply unit 51 is provided.

Hereinafter, exemplary embodiments of a package burn-in test circuit of a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

1 is a view for explaining the application of the power supply voltage for the package burn-in test according to an embodiment of the present invention, Figure 2 is a circuit diagram of a voltage level detector for detecting a voltage applied to an external pin as applied to the present invention FIG. 3 is a circuit diagram of an enable signal generator for package testing, and FIG. 4 is a circuit diagram related to a circuit for generating control signals applied to FIG. 1, and FIG. 5 is a circuit diagram of FIGS. The operation timing of the various signals shown is shown.

For convenience of description, a new PBI test method and a power application method according to the present invention will be described with reference to FIG. In the PBI test, enabling of all the word lines in FIG. 1 can be implemented by supplying a charge of the power supply voltage level to the word lines. In order to do this, an external control signal capable of recognizing a PBI state must be applied to an external pin of the package. In this case, since there is no extra pin in the package state, it is difficult to apply power. Accordingly, in the present invention, in order to secure the extra pin, the WCBR (WE CAS Before RAS: low address strobe bar signal) transitions to the low state, and the write enable signal and the column address strobe bar signal first transition to the low state first. In this case, the memory enters the parallel test mode under timing, not the read or write mode. A don't care state is made, and the A0 and A1 pins are used as external power supply pins.

In addition, the output enable pin OEB is used for light cycles during PBI testing. In FIG. 2, a circuit of a voltage level detector for detecting a voltage applied to an external pin to generate a test clock is shown. After entering the memory into the parallel test mode under the WCBR timing, a 'high' voltage is applied to the output enable pin OEB pin to generate the mast clock PPBESVOE necessary for PBI test in the memory using the circuit of FIG. Let's do it. In FIG. 2, the output enable pin OEB corresponds to the pad PAD. In addition, in the case where the pad PAD is A0 and A1 pins, as in the case of the OEB pin, a 'high' voltage is also applied to control whether the even and odd word lines are enabled. Mast clocks PPBESVA0 and PPBESVA1 are generated. Here, the roles of the OE, A0 and A1 pins may be changed.

As shown in FIG. 1, in the embodiment of the present invention, word line drivers are arranged in pairs, various control signals are generated by the circuits of FIGS. 3 and 4, and applied to the circuit portions 50 and 51 of FIG. The word lines are alternately enabled in odd and even numbers. The reason for this alternation test is to enable one side of the two word lines to screen potential micro bridges that may occur between the word lines to make a potential difference between the word lines. Of course, if the separation between even and odd word lines is unnecessary to simplify the test, only the A0 pin may be used for the PBI test. Reference numeral 50 in FIG. 1 denotes a power supply unit comprising a diode and a control switch for transferring a VCC charge to a word line, and reference numeral 51 shows an example of a charge supply unit for transferring a VCC charge to a word line. The charge supply unit 51 maintains the WBEVSS node at the level of the ground voltage VSS in the normal operation mode to be used as the ground voltage source of the word line driver, and in the PBI test mode, the WBEVSS node is worded by the PPBE and PPBE 1,2 signals. Change to line enable voltage level. As a result, the charge supply unit 51 causes the VCC difference applied in the parallel test mode under the WCBR timing to be supplied to the word lines through the global and local lines GLE, GL0, LL1E, and LL10. At this time, the word line enable level by the charge supplied by the VCC has a disadvantage that it is difficult to accurately ensure the enable level of the word line required in the conventional FBI test, the device by the operation of the memory during the PBI test The word line stress effect is maintained as it is supplemented to some extent by the DC voltage level for the word line made in the internal circuit of the circuit. As a result, the conventional WBI test method can be applied to the PBI test to obtain a faster test. This is because in the embodiment of the present invention, it is possible to externally supply a voltage required for enabling all word lines.

For example, if a 20-hour PBI test is performed on a memory device with 2 kilo refresh at 16 mega DRAM, the total stress applied time to each word line is about 20 seconds. However, when this is applied to the PBI test according to an embodiment of the present invention, a PBI test effect of 20 seconds or 40 seconds can obtain the same 20-hour PBI test effect. As a result, it can be seen that the test time is significantly reduced compared to the burn-in test of the conventional package state.

Describe the overall operation. 5 shows the operation timing of various signals shown in FIGS. 1 to 4 in the test mode according to the present invention. First, external control signals applied to the memory low address strobe bar signal And column address strobe bar signals , Light enable signal When the timing of the corresponding waveform of FIG. 5 is equal to the timing of the WCBR, the memory enters the parallel test mode. The signal? WCBRB, which allows the circuit of FIG. 1 to recognize this parallel test mode, is generated by FIG. 3a. The waveform øRFHB of FIG. 5 shown in FIG. 3a is Enable point of time A clock signal that activates when it is earlier than the enable time, indicating a refresh mode. The waveform? FTE of FIG. 5 generated by FIG. 3b is an abbreviation of the fast test enable signal and is a signal used for normal parallel testing. ØR, øC, øRD, øD PX, øEW are shown in Figs. 3a and 3b, respectively. A clock signal indicating the state of A clock signal for indicating the state of?, A delay signal for? R, a low decoder precharge signal, and a write control clock signal for indicating the write enable state. The waveform PPBE of FIG. 5 applied to FIG. 1 is generated by the NAND gate and inverter of FIG. 4a, the waveform PPBE1 of FIG. 5 is generated by FIG. 4b, and the waveform PPBE2 is generated by FIG. The waveform WBEVSS of FIG. 5 is generated by the charge supply 51 of FIG. 1, and the drawn voltage is applied to the word line WL.

The operation will be described again with the low address strobe signal. And column address strobe signal When is enabled, the clock signals? R and? C informing the state of the signals in FIG. 3a become 'high'. Accordingly, the control signal øRFHB is changed from 'high' to 'low'. For reference, the control signal øRFHB is a column address strobe signal. Low address strobe signal When activated more quickly, it is enabled as 'low'. In addition, the natural signal? RD of the clock signal? R becomes 'high', and the write enable signal The øWCBRB transitions from 'high' to 'low' as the signal øEW is synchronized to 'high'. In FIG. 3B, the enable signal? FTE becomes 'high' as the? WCBRB becomes 'low'. Through the above process, the initial state for the PBI test is set.

In this state, the circuits shown in Figs. 4A, 4B, and 4C enable the control signals PPBE, PPBE1, and PPBE2 to the 'high' state according to the situation. All word lines are enabled and activated with all control signals PPBE, PPBE1, and PPBE2 'high' to run the test simultaneously. In order to activate and test only the even word line, only PPBE1 of FIG. 4b is 'high', and conversely, only PPBE2 of FIG. 4c is 'high' to activate and test only the word word line.

When referring to the technical aspects to be considered in enabling all word lines, the internal delay time for charging and discharging the total word line loading must be guaranteed internally. Since it is difficult to realize, it can be easily implemented by using a long cycle output such as an oscillator for cell refresh or a back bias pumping oscillator.

As described above, according to the present invention, since all word lines can be enabled at the same time by using a power supply voltage in a package state, a package burn-in test can be performed in the same way as a wafer burn-in, and a quick burn-in test in a package state can be performed. By having the effect of executing an operation, the test time can be shortened, thereby reducing the product cost.

Claims (4)

A package burn-in test circuit of a semiconductor memory device, comprising: a plurality of pins for receiving a voltage of a predetermined level in a package state and a voltage for detecting voltages applied to the plurality of pins and generating test clock signals in a predetermined mode. A power supply unit comprising a level detector, an enable signal generation circuit for generating enable signals for package test by combining the test clock signals and signals generated in internal circuits in the mode, and a diode and a control switch. And a charge supply unit 51 for receiving a power supply through the power supply and receiving the enable signals of the enable signal generation circuit to generate a predetermined test voltage and simultaneously apply the same to a plurality of word lines. Package burn-in test circuit of semiconductor memory device. The package burn-in test circuit of claim 1, wherein the pin is an address pin or an output enable pin. The package burn-in test circuit of claim 1, wherein the predetermined mode is a WCBR mode for testing multi-bits. The package burn-in test circuit of claim 1, wherein the plurality of word lines are all word lines or half word lines of the memory.