KR970029872A - Clock Generation Circuit of Nonvolatile Semiconductor Device - Google Patents

Clock Generation Circuit of Nonvolatile Semiconductor Device Download PDF

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Publication number
KR970029872A
KR970029872A KR1019950039742A KR19950039742A KR970029872A KR 970029872 A KR970029872 A KR 970029872A KR 1019950039742 A KR1019950039742 A KR 1019950039742A KR 19950039742 A KR19950039742 A KR 19950039742A KR 970029872 A KR970029872 A KR 970029872A
Authority
KR
South Korea
Prior art keywords
generation circuit
signal
clock generation
clock
rom
Prior art date
Application number
KR1019950039742A
Other languages
Korean (ko)
Inventor
장석현
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950039742A priority Critical patent/KR970029872A/en
Publication of KR970029872A publication Critical patent/KR970029872A/en

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Abstract

본 발명은 반도체 메모리 장치의 클럭발생회로에 관한 것으로서, 특히 어드레스 신호에 응답하여 복수의 롬블럭들에 선택적으로 클럭신호를 공급하는 클럭발생회로에 있어서, 어드레스 신호와 클럭신호를 입력하고 파워다운 신호에 응답하여 파워 다운시에는 상기 롬블럭에 인가되는 클럭신호를 하이상태로 유지하여 프리차지 모드로 유지시키는 것을 특징으로 한다. 따라서, 롬회로의 출력버퍼에서의 누설전류를 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit of a semiconductor memory device, and more particularly, to a clock generation circuit for selectively supplying a clock signal to a plurality of ROM blocks in response to an address signal, wherein the address signal and the clock signal are inputted, and a power down signal is input. In response to the power down, the clock signal applied to the rom block is maintained in a high state to maintain the precharge mode. Therefore, leakage current in the output buffer of the ROM circuit can be prevented.

Description

불휘발성 반도체 장치의 클럭 발생회로Clock Generation Circuit of Nonvolatile Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명에 의한 롬의 클럭 발생회로의 구성을 나타낸 회로도.4 is a circuit diagram showing a configuration of a clock generation circuit of a ROM according to the present invention.

Claims (1)

어드레스 신호에 응답하여 복수의 롬블럭들에 선택적으로 클럭신호를 공급하는 클럭발생회로에 있어서, 어드레스 신호와 클럭신호를 입력하고 파워다운 신호에 응답하여 파워 다운시에는 상기 롬블럭 인가되는 클럭신호를 하이상태로 유지하여 프리차지 모드로 유지시키는 것을 특징으로 하는 롬의 클럭발생회로.A clock generation circuit for selectively supplying a clock signal to a plurality of romblocks in response to an address signal, wherein the clock signal applied to the romblock is input when an address signal and a clock signal are input and the power down signal is turned down in response to a power-down signal. A clock generation circuit of a ROM, characterized by being kept in a high state and held in a precharge mode.
KR1019950039742A 1995-11-04 1995-11-04 Clock Generation Circuit of Nonvolatile Semiconductor Device KR970029872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950039742A KR970029872A (en) 1995-11-04 1995-11-04 Clock Generation Circuit of Nonvolatile Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950039742A KR970029872A (en) 1995-11-04 1995-11-04 Clock Generation Circuit of Nonvolatile Semiconductor Device

Publications (1)

Publication Number Publication Date
KR970029872A true KR970029872A (en) 1997-06-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950039742A KR970029872A (en) 1995-11-04 1995-11-04 Clock Generation Circuit of Nonvolatile Semiconductor Device

Country Status (1)

Country Link
KR (1) KR970029872A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100578112B1 (en) * 1998-10-16 2006-07-25 삼성전자주식회사 Computer system and method controlled memory clock signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100578112B1 (en) * 1998-10-16 2006-07-25 삼성전자주식회사 Computer system and method controlled memory clock signal

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