KR970029823A - Pumping voltage generating circuit - Google Patents

Pumping voltage generating circuit Download PDF

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Publication number
KR970029823A
KR970029823A KR1019950043519A KR19950043519A KR970029823A KR 970029823 A KR970029823 A KR 970029823A KR 1019950043519 A KR1019950043519 A KR 1019950043519A KR 19950043519 A KR19950043519 A KR 19950043519A KR 970029823 A KR970029823 A KR 970029823A
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KR
South Korea
Prior art keywords
node
predetermined
voltage level
voltage
power supply
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Application number
KR1019950043519A
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Korean (ko)
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KR0157294B1 (en
Inventor
이규찬
심재훈
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김광호
삼성전자 주식회사
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Priority to KR1019950043519A priority Critical patent/KR0157294B1/en
Publication of KR970029823A publication Critical patent/KR970029823A/en
Application granted granted Critical
Publication of KR0157294B1 publication Critical patent/KR0157294B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야 :1. The technical field to which the invention described in the claims belongs:

본 발명은 반도체 메모리장치내부의 동작전원전압보다 높은 레벨로 승압된 펌핑전압을 발생하는 반도체 메모리장치의 펌핑전압 발생회로에 관한 것이다.The present invention relates to a pumping voltage generation circuit of a semiconductor memory device for generating a pumping voltage boosted to a level higher than an operating power supply voltage inside the semiconductor memory device.

2. 발명은 해결하려고 하는 기술적 과제 : 종래의 반도체 메모리장치에서 전원전압 VCC가 2볼트이상인 경우, 2VCC를 VCC+1.5볼트로 만드는 것은 어렵지 않다. 그러나 전원전압 VCC가 1.5볼트이하의 저전원전압상태에서는 2VCC를 VCC+1.5볼트로 만드는 것은 그리 용이하지 않다. 따라서 저전원전압상태에서 높게 승압된 전압레벨을 출력하는 것이 본 발명의 과제이다.2. The technical problem to be solved by the present invention: In the conventional semiconductor memory device, when the power supply voltage VCC is 2 volts or more, it is not difficult to make 2VCC into VCC + 1.5 volts. However, it is not very easy to make 2VCC VCC + 1.5 volts when the supply voltage VCC is under 1.5 volts. Accordingly, it is a problem of the present invention to output a voltage level that is elevated in a low power supply state.

3. 발명의 해결방법의 요지 : 초기상태에서 소정의 제1노드를 전원전압레벨로 프리차아지하는 프리차아지수단과, 소정의 제1클럭신호를 응답하여 상기 제1노드의 전압레벨을 소정의 제1전압레벨로 승압하는 제1승압수단과, 소정의 제2클럭신호에 응답하여 상기 제1노드와 소정의 제2노드를 선택적으로 접속하여 상기 제1노드의 전압을 제2노드로 전달을 선택적으로 제어하는 제1전송수단과, 소정의 제3클럭신호에 응답하여 상기 제2노드의 전압레벨을 소정의 제2전압레벨로 2차승압하는 제2승압수단과, 소정의 제4클럭신호에 응답하여 상기 제2노이드의 제2전압레벨을 출력단으로 전송하는 제2전송수단을 구비함을 특징으로 하는 반도체 메모리장치의 펌핑전압 발생회로를 구현하므로써 상기 과제를 달성하게 된다.3. Summary of the Invention A precharge means for precharging a predetermined first node to a power supply voltage level in an initial state, and a predetermined voltage level of the first node in response to a predetermined first clock signal. A first boosting means for boosting to a first voltage level, and selectively connecting the first node and a predetermined second node in response to a predetermined second clock signal to transfer the voltage of the first node to the second node; A first transmission means for selectively controlling, second boosting means for secondly boosting the voltage level of the second node to a predetermined second voltage level in response to a predetermined third clock signal, and a predetermined fourth clock signal The above object is achieved by implementing a pumping voltage generation circuit of a semiconductor memory device, characterized in that it comprises a second transfer means for transmitting the second voltage level of the second node to an output terminal in response to the second node.

4. 발명의 중요한 용도 : 저전원전압에서 소망하는 펌핑전압을 출력하는 반도체 메모리장치.4. Important use of the invention: semiconductor memory device that outputs a desired pumping voltage at a low power supply voltage.

Description

펌핑전압 발생회로Pumping voltage generating circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 펌핑전압 발생회로의 회로도2 is a circuit diagram of a pumping voltage generation circuit according to the present invention.

Claims (5)

반도체 메모리장치의 펌핑전압 발생회로에 있어서, 초기상태에서 소정의 제1노드를 전원전압레벨로 프리차아지하는 프리차아지수단과, 소정의 제1클럭신호에 응답하여 상기 제1노드의 전압레벨을 소정의 제1전압레벨로 승압하는 제1승압수단과, 소정의 제2클럭신호에 응답하여 상기 제1노드와 소정의 제2노드를 선택적으로 접속하여 상기 제1노드의 전압을 제2노드로 전달을 선택적으로 제어하는 제1전송수단과, 소정의 제3클럭신호에 응답하여 상기 제2노드의 전압레벨을 소정의 제2전압레벨로 2차승압하는 제2승압수단과, 소정의 제4클럭신호에 응답하여 상기 제2노드의 제2전압레벨을 출력단으로 전송하는 제2전송수단을 구비함을 특징으로 하는 반도체 메모리장치의 펌핑전압 발생회로.A pumping voltage generation circuit of a semiconductor memory device, comprising: precharge means for precharging a predetermined first node to a power supply voltage level in an initial state, and a voltage level of the first node in response to a predetermined first clock signal. First boosting means for boosting to a predetermined first voltage level, and selectively connecting the first node to a predetermined second node in response to the predetermined second clock signal to transfer the voltage of the first node to the second node; First transmission means for selectively controlling transmission, second boosting means for secondly boosting the voltage level of the second node to a predetermined second voltage level in response to a predetermined third clock signal, and a predetermined fourth And a second transfer means for transmitting a second voltage level of the second node to an output terminal in response to a clock signal. 제1항에 있어서, 상기 제1전압레벨이 전원전압레벨의 1.5배임을 특징으로 하는 반도체 메모리장치의 펌핑전압 발생회로.The pumping voltage generation circuit of claim 1, wherein the first voltage level is 1.5 times a power supply voltage level. 제1항에 있어서, 상기 제2전압레벨이 전원전압레벨의 2.5배임을 특징으로 하는 반도체 메모리장치의 펌핑전압 발생회로.2. The pumping voltage generation circuit of claim 1, wherein the second voltage level is 2.5 times the power supply voltage level. 제1항에 있어서, 상기 제1전송수단과 제2전송수단이 각각 피모오스 트랜지스터임을 특징으로 하는 반도체 메모리장치의 펌핑전압 발생회로.The pumping voltage generation circuit of a semiconductor memory device according to claim 1, wherein the first transfer means and the second transfer means are PMOS transistors, respectively. 제4항에 있어서, 상기 피모오스 트랜지스터가 소정의 승압전압보다 높은 전압이 웰바이어스로 인가됨을 특징으로 하는 반도체 메모리장치의 펌핑전압 발생회로.The pumping voltage generation circuit of claim 4, wherein a voltage higher than a predetermined boost voltage is applied to the PMOS transistor as a well bias.
KR1019950043519A 1995-11-24 1995-11-24 Pumping voltage making circuit KR0157294B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950043519A KR0157294B1 (en) 1995-11-24 1995-11-24 Pumping voltage making circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950043519A KR0157294B1 (en) 1995-11-24 1995-11-24 Pumping voltage making circuit

Publications (2)

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KR970029823A true KR970029823A (en) 1997-06-26
KR0157294B1 KR0157294B1 (en) 1998-12-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100732253B1 (en) * 2002-07-11 2007-06-25 주식회사 하이닉스반도체 Boosting circuit of semiconductor apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100732253B1 (en) * 2002-07-11 2007-06-25 주식회사 하이닉스반도체 Boosting circuit of semiconductor apparatus

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KR0157294B1 (en) 1998-12-01

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