CA2243375A1 - High voltage generating circuit for volatile semiconductor memories - Google Patents

High voltage generating circuit for volatile semiconductor memories Download PDF

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Publication number
CA2243375A1
CA2243375A1 CA 2243375 CA2243375A CA2243375A1 CA 2243375 A1 CA2243375 A1 CA 2243375A1 CA 2243375 CA2243375 CA 2243375 CA 2243375 A CA2243375 A CA 2243375A CA 2243375 A1 CA2243375 A1 CA 2243375A1
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CA
Canada
Prior art keywords
node
voltage
circuit
boost
pump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA 2243375
Other languages
French (fr)
Other versions
CA2243375C (en
Inventor
Jieyan Zhu
Valerie Lines
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TRACESTEP HOLDINGS LLC
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Priority to CA 2243375 priority Critical patent/CA2243375C/en
Publication of CA2243375A1 publication Critical patent/CA2243375A1/en
Application granted granted Critical
Publication of CA2243375C publication Critical patent/CA2243375C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Dram (AREA)

Abstract

A high voltage generating circuit which provides a constant V PP output without any threshold voltage drop and which does not suffer from latch-up problems is described. Thus a voltage boosting circuit which provides for a boosted voltage V PP at an output node, from a supply voltage V DD, includes a precharge transistor element responsive to a precharge clock signal for transferring the supply voltage V
DD to a boost node for precharging the boost node to the full supply voltage V DD. The circuit further includes a capacitive element connected between the boost node and a pump node, the capacitive element pumping the boost node in response to a pump voltage signal applied to the pump node; and a switching element connected between the boost node and the output node, for transferring charge from the capacitive element to the output node to provide the boosted voltage V PP. In particular the precharge transistor element is an PMOS transistor. Furthermore in order to prevent latch-up of the PMOS devices, a switching circuit is provided to maintain the substrate at the highest voltage in the circuit.
CA 2243375 1998-07-16 1998-07-16 High voltage generating circuit for volatile semiconductor memories Expired - Fee Related CA2243375C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA 2243375 CA2243375C (en) 1998-07-16 1998-07-16 High voltage generating circuit for volatile semiconductor memories

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA 2243375 CA2243375C (en) 1998-07-16 1998-07-16 High voltage generating circuit for volatile semiconductor memories

Publications (2)

Publication Number Publication Date
CA2243375A1 true CA2243375A1 (en) 2000-01-16
CA2243375C CA2243375C (en) 2005-09-13

Family

ID=29409645

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2243375 Expired - Fee Related CA2243375C (en) 1998-07-16 1998-07-16 High voltage generating circuit for volatile semiconductor memories

Country Status (1)

Country Link
CA (1) CA2243375C (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9584118B1 (en) 2015-08-26 2017-02-28 Nxp Usa, Inc. Substrate bias circuit and method for biasing a substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9584118B1 (en) 2015-08-26 2017-02-28 Nxp Usa, Inc. Substrate bias circuit and method for biasing a substrate
EP3136198A1 (en) * 2015-08-26 2017-03-01 NXP USA, Inc. Substrate bias circuit and method for biasing a substrate

Also Published As

Publication number Publication date
CA2243375C (en) 2005-09-13

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Legal Events

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EEER Examination request
MKLA Lapsed