KR970024736A - Interprocessor communication device for triplex network. - Google Patents

Interprocessor communication device for triplex network. Download PDF

Info

Publication number
KR970024736A
KR970024736A KR1019950037120A KR19950037120A KR970024736A KR 970024736 A KR970024736 A KR 970024736A KR 1019950037120 A KR1019950037120 A KR 1019950037120A KR 19950037120 A KR19950037120 A KR 19950037120A KR 970024736 A KR970024736 A KR 970024736A
Authority
KR
South Korea
Prior art keywords
network
hdlc
receiving
system ram
processor
Prior art date
Application number
KR1019950037120A
Other languages
Korean (ko)
Other versions
KR0179587B1 (en
Inventor
김주용
Original Assignee
유기범
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 유기범, 대우통신 주식회사 filed Critical 유기범
Priority to KR1019950037120A priority Critical patent/KR0179587B1/en
Publication of KR970024736A publication Critical patent/KR970024736A/en
Application granted granted Critical
Publication of KR0179587B1 publication Critical patent/KR0179587B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC

Abstract

본 발명에 따라 3중화된 망동기장치는 프로세서간 통신장치를 각각 구비하고 있는 바, 이 프로세서간 통신장치는 망동기장치를 제어하기 위한 프로세서부(41); 다른 두개의 망동기장치에 자신의 IPC데이타를 송신하기 위한 송신 메모리와 다른 두개의 망동기장치로 IPC데이타를 수신하기 위한 수신메모리 영역을 할당하기 위한 이중포트 시스템 램(42); 상기 시스템 램(42)에 저장된 데이타를 HDLC프로토콜에 따라 송신 및 수신하기 위한 제1 HDLC제어기(43); 상기 시스템 램에 저장된 데이타를 HDLC프로토콜에 따라 수신하기 위한 제2 HDLC제어기(44); 및 상기 제1 HDLC제어기 및 제2HDLC제어기에 의한 송수신 데이타를 일시 저정하며, 프로세서로부터 입력된 기능선택(SEL) 신호에 따라 루프백기능이 활성화되면 자신의 송신 IPC 데이타를 수신측으로 루프백시키도록 된 외부버퍼(45)가 구비된다. 따라서 신속하게 상태정보를 획득할 수 있으며 통신의 신뢰성을 향상시킬 수 있는 효과가 있다.The triplex network synchronizer device according to the present invention includes a processor-to-processor communication device, which includes a processor unit 41 for controlling the network device; A dual port system RAM 42 for allocating a transmission memory for transmitting its IPC data to the other two network devices and a receiving memory area for receiving IPC data with the other two network devices; A first HDLC controller 43 for transmitting and receiving data stored in the system RAM 42 according to the HDLC protocol; A second HDLC controller 44 for receiving data stored in the system RAM according to the HDLC protocol; And an external buffer configured to temporarily store transmission / reception data by the first HDLC controller and the second HDLC controller, and to loop back its own transmission IPC data to a receiving side when the loopback function is activated according to a function selection (SEL) signal input from the processor. 45 is provided. Therefore, the status information can be obtained quickly and the reliability of communication can be improved.

Description

망동기 3중화를 위한 프로세서간 통신장치.Interprocessor communication device for triplex network.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따라 망동기를 3중화할 경우 프로세서간 통신장치를 도시한 블럭도,2 is a block diagram showing an interprocessor communication apparatus when triplexing a network synchronizer according to the present invention;

제3도는 제2도에 도시된 일 프로세서의 통신계통을 도시한 블럭도,3 is a block diagram showing a communication system of one processor shown in FIG.

제4도는 본 발명을 설명하기 위해 도시한 HDLC 프로토콜에 따른 데이타 포맷도,4 is a data format diagram according to the HDLC protocol shown to illustrate the present invention,

제5도는 제3도에 도시된 외부버퍼의 루프백을 위한 회로도이다.5 is a circuit diagram for loopback of the external buffer shown in FIG.

Claims (3)

제1망동기장치와 제2망동기장치 및 제3망동기장치가 서로 IPC데이타를 교환하므로써 상대방의 상태정보를 인지하여 망동기장치를 3중화할 수 있도록 된 디지탈 전전자교환기의 망동기 3중화장치에 있어서, 망동기장치를 제어하기 위한 프로세서부(41); 다른 두개의 망동기장치에 자신의 IPC데이타를 송신하기 위한 송신 메모리와 다른 두개의 망동기장치로 IPC데이타를 수신하기 위한 수신메모리 영역을 할당하기 위한 이중포트 시스템 램(42); 상기 시스템 램(42)에 저장된 데이타를 HDLC프로토콜에 따라 송신 및 수신하기 위한 제1 HDLC제어기(43); 상기 시스템 램에 저장된 데이타를 HDLC프로토콜에 따라 수신하기 위한 제2 HDLC제어기(44); 및 상기 제1 HDLC제어기 및 제2HDLC제어기에 의한 송수신 데이타를 일시 저정하며, 프로세서로부터 입력된 기능선택(SEL) 신호에 따라 루프백기능이 활성화되면 자신의 송신 IPC데이타를 수신측으로 루프백시키도록 된 외부버퍼(45)가 구비되는 망동기 3중화를 위한 프로세서간 통신장치.The network synchronizer of the digital electronic switchgear is capable of triplexing the network synchronizer by recognizing the status information of the other party by exchanging IPC data between the first network synchronizer and the second network synchronizer. An apparatus comprising: a processor unit (41) for controlling a network synchronizer device; A dual port system RAM 42 for allocating a transmission memory for transmitting its IPC data to the other two network devices and a receiving memory area for receiving IPC data with the other two network devices; A first HDLC controller 43 for transmitting and receiving data stored in the system RAM 42 according to the HDLC protocol; A second HDLC controller 44 for receiving data stored in the system RAM according to the HDLC protocol; And an external buffer configured to temporarily store transmission / reception data by the first HDLC controller and the second HDLC controller, and to loop back its own transmission IPC data to the receiving side when the loopback function is activated according to a function selection (SEL) signal input from the processor. Inter-processor communication device for the network-operator triplet provided with (45). 제1항에 있어서, 상기 프로세서부(41), 이중포트 시스템 램(42), 제1HDLC 내지 제2HDLC(43,44)는 모토롤라사의 MC68302 마이크로 프로세서로 구현되는 것을 특징으로 하는 망동기 3중화를 위한 프로세서간 통신장치.The method of claim 1, wherein the processor unit 41, dual-port system RAM 42, the first HDLC to 2 HDLC (43, 44) is a motor for the triplex of the manipulator, characterized in that implemented by the MC68302 microprocessor Interprocessor communication device. 제1항에 있어서, 상기 외부버퍼(45)는 반전된 선택신호와 자신의 송신신호를 논리합 하는 제1앤드게이트(52)와, 반전되지 않은 선택신호와 수신신호를 논리합하는 제2앤드게이트(53), 상기 제1앤드게이트(52)의 출력과 제2앤드게이트(53)의 출력을 논리곱하는 오아게이트(54)를 포함하여 구성되는 것을 특징으로 하는 망동기 3중화를 위한 프로세서간 통신장치.The external buffer 45 of claim 1, wherein the external buffer 45 includes a first and gate 52 for ORing the inverted selection signal and its own transmission signal and a second and gate for ORing the inverted selection signal and the received signal. 53), an interprocessor communication apparatus for triplexing a network, characterized in that it comprises an oragate 54, the logical AND of the output of the first and gate 52 and the output of the second and gate 53. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950037120A 1995-10-25 1995-10-25 An inter-processor communication apparatus for synchronizing network KR0179587B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950037120A KR0179587B1 (en) 1995-10-25 1995-10-25 An inter-processor communication apparatus for synchronizing network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950037120A KR0179587B1 (en) 1995-10-25 1995-10-25 An inter-processor communication apparatus for synchronizing network

Publications (2)

Publication Number Publication Date
KR970024736A true KR970024736A (en) 1997-05-30
KR0179587B1 KR0179587B1 (en) 1999-05-15

Family

ID=19431301

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950037120A KR0179587B1 (en) 1995-10-25 1995-10-25 An inter-processor communication apparatus for synchronizing network

Country Status (1)

Country Link
KR (1) KR0179587B1 (en)

Also Published As

Publication number Publication date
KR0179587B1 (en) 1999-05-15

Similar Documents

Publication Publication Date Title
KR960006642A (en) Enhanced Peripherals for Use in Multimedia Conferencing Systems
KR930702837A (en) Method and device for data transmission for communication between peripheral device and master device
KR950033863A (en) I / O system based on intelligent memory
KR970024736A (en) Interprocessor communication device for triplex network.
KR960039740A (en) Electronic apparatus and communication control method thereof
KR910003475A (en) Sequence controller
KR950022597A (en) Inter-processor communication device using PIPO memory
KR940002722A (en) Data transfer and synchronization method between CPUs in a system consisting of two CPUs
JPS615654A (en) Initial setting system of digital line terminator
KR970056479A (en) Matching device for communication between processors
JPS63211860A (en) Facsimile equipment
KR20020055855A (en) Method for receiving atm data between processer and processer in mobile bts system
KR970019236A (en) (APPARATUS FOR RECEIVING / SENDING IPC MESSAGE IN THE SWITCHING SYSTEM USING ATM AND METHOD)
KR940027458A (en) Facsimile implementation circuit and control method for transmitting information of general purpose computer
KR900008883A (en) X-loading method of electronic control system of distributed control system
KR960025102A (en) Processor for connecting electronic electronic switch
JPS62125736A (en) Data transfer equipment
KR930015933A (en) Primary Line Termination Board
KR960020102A (en) Multiple Serial Interfaces for Wireless Public Telephones
JPS62235845A (en) File transmission and reception system using electronic mail
KR920005558A (en) Implementation Method of User Information Function of Integrated Telecommunication Network in Electronic Switching System
KR900004132A (en) Data transfer method of data exchange
KR960016307A (en) Device and method for connecting digital key phone in digital key phone system
KR920016958A (en) How to load subscriber mounting information
KR930014208A (en) Signal message processing method using common line signaling method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20121031

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20131022

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee