KR970024301A

KR970024301A - Thin film transistor manufacturing method

Info

Publication number: KR970024301A
Application number: KR1019950035178A
Authority: KR
Inventors: 정종인
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-10-12
Filing date: 1995-10-12
Publication date: 1997-05-30

Abstract

본 발명은 게이트와 Data의 cross over부 내부에 에치 스토퍼와 a-Si 패턴을 self-align 형성법에 관한 것으로, 더 자세하게는 액티브 패턴을 위한 포토공정을 하지 않고 게이트 메탈을 이용한 Back 노광으로 셀프 얼라인 방식으로 노광량을 조절하여 에치 스토퍼막과 액티브 패턴을 형성하는 방법이다. 본 발명의 self-align에 의한 형성법은 a-Si 막이 게이트 메탈만을 덮는 구조를 가지며, 또한 기존의 공정에서 Back 노광에 의한 액티브 패턴의 형성과 n -Si 증착과정을 맞바꾼 제작공정에 의해 구현되었다.The present invention relates to a method of self-aligning an etch stopper and an a-Si pattern inside a cross over portion of a gate and data, and more specifically, self-aligning by back exposure using a gate metal without performing a photo process for an active pattern. The exposure amount is controlled in a manner to form an etch stopper film and an active pattern. The self-aligning method of the present invention has a structure in which the a-Si film covers only the gate metal, and is implemented by a fabrication process in which an active pattern is formed by back exposure and an n-Si deposition process is exchanged in a conventional process.

Description

Thin film transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 형성법에 의한 크로스 오버부의 단면도와 평면도, 그리고 박막 트랜지스터 채널부의 단면도.2 is a cross-sectional view and a plan view of a crossover section and a thin film transistor channel section according to the forming method of the present invention.

Claims

Forming a gate electrode 13 on the transparent glass substrate 14, depositing a nitride film 12 on the gate electrode 13, and depositing an amorphous silicon 11 layer on the nitride film 12. Forming a etch stopper pattern 10 by a first back exposure on the deposited nitride film, and forming an etch stopper pattern 10 on the deposited nitride film. Forming an active pattern 11 by a second back exposure, depositing an n si layer 9 on the active pattern 11, and depositing a data line on the n si layer 9. And forming a data line pattern (8) in said data line.

The method of claim 1, wherein when performing the back exposure of the etch stopper film 10 and the active pattern 11, the etch stopper pattern 10 is first back exposed and then the active pattern 11 is back exposed. A method of manufacturing a thin film transistor, characterized in that the amount of exposure is controlled to be formed on the gate line and the active pattern (11) is formed outside the etch stopper pattern (10).

The method of claim 1, wherein the active pattern (11) is subjected to back exposure without using an active mask separately.

※ Note: The disclosure is based on the initial application.