KR970023878A - Semiconductor manufacturing method - Google Patents

Semiconductor manufacturing method Download PDF

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Publication number
KR970023878A
KR970023878A KR1019950037736A KR19950037736A KR970023878A KR 970023878 A KR970023878 A KR 970023878A KR 1019950037736 A KR1019950037736 A KR 1019950037736A KR 19950037736 A KR19950037736 A KR 19950037736A KR 970023878 A KR970023878 A KR 970023878A
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South Korea
Prior art keywords
silicon film
transistor
forming
film
semiconductor manufacturing
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KR1019950037736A
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Korean (ko)
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KR0167667B1 (en
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김천수
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김주용
현대전자산업주식회사
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Priority to KR1019950037736A priority Critical patent/KR0167667B1/en
Publication of KR970023878A publication Critical patent/KR970023878A/en
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Publication of KR0167667B1 publication Critical patent/KR0167667B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Abstract

본 발명은 적어도 하나의 트랜지스터를 구비하는 반도체 소자에서, 상기 트랜지스터의 게이트 전극 상부 표면 및 소오스/드레인 상부 표면에 실리사이드막을 형성하기 위한 반도체 제조 방법에 있어서 ; 기형성된 트랜지스터의 게이트 전극 및 소오스/드레인 상부 표면에 선택적 증착으로 실리콘막을 형성하는 단계 ; 상기 실리콘막을 비정질화하는 단계 ; 상기 비정질화된 실리콘막 상에 실리사이드막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 제조 방법에 관한 것으로, 본 발명은 N-MOS지역의 As에 의한 실리사이드 성장 억제를 배제하여 낮은 면저항을 가지며, 소자의 고집적화가 가능하고, N-MOS 지역과 P-MOS지역의 실리사이드막을 균일한 두께로 형성하여 제조 공정이 용이함을 가져오는 효과가 있다.A semiconductor manufacturing method for forming a silicide film on a gate electrode upper surface and a source / drain upper surface of a transistor in a semiconductor device having at least one transistor; Forming a silicon film by selective deposition on the gate electrode and the source / drain top surface of the preformed transistor; Making the silicon film amorphous; The present invention relates to a semiconductor manufacturing method comprising forming a silicide film on the amorphous silicon film. High integration is possible, and the silicide films in the N-MOS region and the P-MOS region are formed to have a uniform thickness, thereby making the manufacturing process easier.

Description

반도체 제조방법Semiconductor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A도 내지 제1D도는 본 발명의 일실시예에 따른 CMOS제조 공정도.1A to 1D are CMOS manufacturing process diagrams according to one embodiment of the present invention.

Claims (11)

적어도 하나의 트랜지스터를 구비하는 반도체 소자에서, 상기 트랜지스터의 게이트 전극 상부 표면 및 소오스/드레인 상부 표면에 실리 사이드막을 형성하기 위한 반도체 제조 방법에 있어서 ; 기형성된 트랜지스터의 게이트 전극 및 소오스/드레인 상부 표면에 선택적 증착으로 실리콘막을 형성하는 단계 ; 상기 실리콘막을 비정질화하는 단계 ; 및 상기 비정질화된 실리콘막 상에 실리사이드막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 제조 방법.A semiconductor device comprising at least one transistor, comprising: a semiconductor manufacturing method for forming a silicide film on an upper surface of a gate electrode and a source / drain upper surface of the transistor; Forming a silicon film by selective deposition on the gate electrode and the source / drain top surface of the preformed transistor; Making the silicon film amorphous; And forming a silicide film on the amorphous silicon film. 제1항에 있어서 ; 상기 트랜지스터는 N-MOS인 것을 특징으로 하는 반도체 제조 방법.The method of claim 1; Wherein said transistor is an N-MOS. 제1항에 있어서 ; 상기 트랜지스터는 CMOS로 이루어지는 것을 특징으로 하는 반도체 제조 방법.The method of claim 1; And the transistor is made of CMOS. 제2항 또는 제3항에 있어서 ; 상기 N-MOS의 소오스/드레인은 As이 이온주입된 영역인 것을 특징으로 하는 반도체 제조 방법.The method of claim 2 or 3; The source / drain of the N-MOS is a semiconductor manufacturing method, characterized in that the As implanted region. 제4항에 있어서 ; 상기 실리콘막은 비도핑된 것을 특징으로 하는 반도체 제조 방법.The method of claim 4; And the silicon film is undoped. 제5항에 있어서, 상기 실리콘막은 선택적 증착은 600℃ 내지 700℃의 온도에서 CVD로 이루어지는 것을 특징으로 하는 반도체 제조 방법.The method of claim 5, wherein the silicon film is selectively deposited by CVD at a temperature of 600 ° C. to 700 ° C. 7. 제6항에 있어서 ; 상기 CVD에서 Si2H6가스의 플로우 율을 조정하여 균일한 실리콘막을 형성하는 것을 특징으로 하는 반도체 제조 방법.The method of claim 6; And forming a uniform silicon film by adjusting a flow rate of Si 2 H 6 gas in the CVD. 제4항에 있어서; 상기 실리콘막을 비정질화 하는 단계는, 상기 비도핑된 실리콘막에 이온주입을 실시하여 이루어지는 것을 특징으로 하는 반도체 제조 방법.The method of claim 4; Amorphizing the silicon film, the semiconductor manufacturing method, characterized in that by implanting the undoped silicon film. 제8항에 있어서 ; 상기 비도핑된 실리콘막에 이온주입되는 이온 As 이온인 것을 특징으로 하는 반도체 제조 방법.The method of claim 8; And ion ions implanted into the undoped silicon film. 제1항에 있어서 ; 상기 실리사이드막은 TiSi2인 것을 특징으로 하는 반도체 제조 방법.The method of claim 1; The silicide layer is TiSi 2 , characterized in that the semiconductor manufacturing method. 제10항에 있어서 ; 상기 TiSi2를 형성하는 단계는, 전체구조 상부에 Ti막을 증착하고 제1신터링 하는 단계 ; 상기 Ti막을 선택적 식각하고 제2신터링을 실시하는 단계를 포함하는 것을 특징으로 하는 반도체 제조 방법.The method of claim 10; The forming of TiSi 2 may include depositing and first sintering a Ti film over the entire structure; Selectively etching the Ti film and performing a second sintering process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950037736A 1995-10-27 1995-10-27 Method of fabricating semiconductor KR0167667B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000066155A (en) * 1999-04-13 2000-11-15 황인길 Shallow junction &silicide forming method of semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000066155A (en) * 1999-04-13 2000-11-15 황인길 Shallow junction &silicide forming method of semiconductor devices

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