KR970023853A - Manufacturing method of insulating layer between polysilicon layers - Google Patents

Manufacturing method of insulating layer between polysilicon layers Download PDF

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Publication number
KR970023853A
KR970023853A KR1019950036151A KR19950036151A KR970023853A KR 970023853 A KR970023853 A KR 970023853A KR 1019950036151 A KR1019950036151 A KR 1019950036151A KR 19950036151 A KR19950036151 A KR 19950036151A KR 970023853 A KR970023853 A KR 970023853A
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South Korea
Prior art keywords
forming
layer
organosilane
polysilicon
ozone
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KR1019950036151A
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Korean (ko)
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KR100220225B1 (en
Inventor
수 웬-도에
쿠 치아-린
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훙 치우 후
모셀 비텔릭 인코포레이티드
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Priority to KR1019950036151A priority Critical patent/KR100220225B1/en
Publication of KR970023853A publication Critical patent/KR970023853A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

본 발명의 목적은, 반도체장치의 구조에 중간층 유전체를 발생시키는 방법을 제공함에 있다. 본 발명의 방법은, DRAM구조내에서 의 중간층 유전체를 형성가공하기 위하여 비교적 균일하고도 용이한 방법을 제공한다.An object of the present invention is to provide a method for generating an interlayer dielectric in the structure of a semiconductor device. The method of the present invention provides a relatively uniform and easy method for forming and processing an interlayer dielectric in a DRAM structure.

실질적으로 균일한 중간층 유전체층을 가지는 집적회로의 형성가공법은, 제1폴리실리콘을 가지는 국부적으로 완성된 반도체 웨이퍼(400)를 제공하는 스텝과, 약 1기압의 압력으로 국부적으로 완성된 반도체 장치의 폴리 실리콘층 및 그 부분을 피복하는 유전체층(405)을 침적하는 스텝과, 유전체층의 부분을 피복하여 제2폴리실리콘층을 형성하는 스텝을 구비하는 것으로, 해당 유전체층의 침적스텝은, 200g/m2및 이하의 농도로, 유기실런 및 오존을 결합하여 실행된다.An integrated circuit forming and processing method having a substantially uniform intermediate layer dielectric layer comprises the steps of providing a locally completed semiconductor wafer 400 having a first polysilicon and a poly of a semiconductor device locally completed at a pressure of about 1 atmosphere. And depositing the silicon layer and the dielectric layer 405 covering the portion thereof, and forming the second polysilicon layer by covering the portion of the dielectric layer, wherein the deposition step of the dielectric layer is 200 g / m 2 ; It is performed by combining organosilane and ozone at the following concentrations.

Description

폴리실리콘층간의 절연층의 제조방법Manufacturing method of insulating layer between polysilicon layers

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는, 본 발명에 의한 간략한 형성가공법을 나타낸다.4 shows a simplified forming process according to the present invention.

Claims (7)

제1폴리실리콘층을 그 상부에 가지는 국부적으로 완성된 반도체 장치를 제공하는 스텝과, 약 대기 1기압의 압력으로 상기 국부적으로 완성된 반도체 장치의 부분 및 상기 폴리실리콘층을 피복하는 유전체층을 형성하는 스텝과, 상기 유전체층의 부분을 피복하는 제2폴리실리콘층을 형성하는 스텝을 구비하고, 상기 유전체층 형성스텝은, 유기실런 및 저농도의 오존을 침적하는 스텝을 구비하는 집적회로장치의 형성가공법.Providing a locally completed semiconductor device having a first polysilicon layer thereon, and forming a portion of the locally completed semiconductor device and a dielectric layer covering the polysilicon layer at a pressure of about atmospheric pressure 1 atmosphere; And a step of forming a second polysilicon layer covering a portion of the dielectric layer, wherein the dielectric layer forming step includes a step of depositing an organosilane and a low concentration of ozone. 제1항에 있어서, 상기 유기실런은 테트라에틸옥시실런(TEOS), 헥사메틸디실런(HMDS) 및 옥타메틸시클로테트라실록산(OHCTS)으로 이루어지는 군으로 선택되고, 상기 비교적 저농도는 200g/m2, 150g/m2또는 100g/m2및 이하이며, 상기 유기실런 및 상기 오존은 약 7.5:2.0의 상대유량에 있고, 상기 형성스텝은 약 300℃에서 약 500℃사이, 바람직하게는 약 398℃의 온도로 행해지는 집적회로장치의 형성가공법.The method of claim 1, wherein the organosilane is selected from the group consisting of tetraethyloxysilane (TEOS), hexamethyldisilane (HMDS) and octamethylcyclotetrasiloxane (OHCTS), wherein the relatively low concentration is 200 g / m 2 , 150 g / m 2 or 100 g / m 2 and below, wherein the organosilane and the ozone are at a relative flow rate of about 7.5: 2.0, and the forming step is between about 300 ° C. and about 500 ° C., preferably about 398 ° C. An integrated circuit device forming and processing method performed at a temperature. 제1항에 있어서, 상기 집적회로의 형성가공법은, 약800℃ 또는 약850℃보다도 높은 온도로 상기 국부적으로 완성된 장치를 어닐링하는 스텝을 구비하여 이루어지는 집적회로의 형성가공법.The method of claim 1, wherein the integrated circuit forming and processing method comprises the step of annealing the locally completed device at a temperature higher than about 800 ° C or about 850 ° C. 1기압의 압력으로 유기실런 및 비교적 저농도의 오존을 결합하는 스텝과, 상기 오존 및 상기 유기실런의 혼합물에서 절연층을 형성하는 스텝을 구비함을 특징으로 하는 유전체층 형성방법.And a step of combining the organosilane and the relatively low concentration of ozone at a pressure of 1 atm, and forming an insulating layer from a mixture of the ozone and the organosilane. 제1 폴리실리콘영역 및 전계분리산화물영역의 복수영역을 구비한 국부적으로 완성된 장치를 제공하는 스텝과, 약 1기압의 압력으로 유기실런 및 비교적 저압의 오존을 포함한 혼합물을 포함하는 스텝과, 상기 복수영역을 피복하는 혼합물에서 유전제층을 형성하는 스텝으로 이루어지는 집적회로의 형성방법.Providing a locally completed device having a plurality of zones of a first polysilicon zone and a field separation oxide zone, comprising a mixture comprising an organosilane and a relatively low pressure ozone at a pressure of about 1 atmosphere; A method for forming an integrated circuit comprising a step of forming a dielectric agent layer from a mixture covering a plurality of regions. 제5항에 있어서, 상기 복수영역은 측벽스페이서를 구비하는 집적회로의 형성방법.The method of claim 5, wherein the plurality of regions have sidewall spacers. 제5항에 있어서, 상기 집적회로의 형성방법은, 상기 유전체층을 어닐링 및 에칭하는 스텝과, 상기 폴리실리콘층 및 전계분리산화물층의 부분을 피복하는 제2폴리실리콘영역을 형성하는 스텝과, 상기 제2폴리실리콘영역을 패턴화하는 스텝을 구비하고, 상기 패턴화 스텝은 실질적으로 스트링거나 존재하지 않는 상부 표면을 제공하고, 상기 스트링거는, 상기 제2폴리실리콘영역의 일부에 의하여 한정됨을 특징으로 하는 집적회로 형성 방법.The method of claim 5, wherein the method of forming the integrated circuit comprises: annealing and etching the dielectric layer, forming a second polysilicon region covering a portion of the polysilicon layer and the field separation oxide layer; And patterning the second polysilicon region, the patterning step providing a top surface that is substantially stringed or non-existent, wherein the stringer is defined by a portion of the second polysilicon region. Integrated circuit forming method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950036151A 1995-10-19 1995-10-19 Process for forming interlayer insulator between polysilicon layers KR100220225B1 (en)

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