KR960026588A - Device Separation Method of Semiconductor Devices - Google Patents

Device Separation Method of Semiconductor Devices Download PDF

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Publication number
KR960026588A
KR960026588A KR1019940039056A KR19940039056A KR960026588A KR 960026588 A KR960026588 A KR 960026588A KR 1019940039056 A KR1019940039056 A KR 1019940039056A KR 19940039056 A KR19940039056 A KR 19940039056A KR 960026588 A KR960026588 A KR 960026588A
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South Korea
Prior art keywords
oxide film
trench
pad oxide
forming
nitride film
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KR1019940039056A
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Korean (ko)
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KR100297171B1 (en
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엄금용
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김주용
현대전자산업 주식회사
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Priority to KR1019940039056A priority Critical patent/KR100297171B1/en
Publication of KR960026588A publication Critical patent/KR960026588A/en
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Publication of KR100297171B1 publication Critical patent/KR100297171B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체소자의 소자분리 방법에 관한 것으로서, 제1패드산화막과 제1질화막패턴을 마스크로 반도체기판에서 소자분리영역으로 예정되어 있는 부분을 소정 깊이로 식각하여 트랜치를 형성하고, 상기 구조의 전표면에 TEOS로 된 제1패드산화막과 제2질화막을 상기 트랜치를 메우지 않는 정도의 두께로 형성하고, 상기 트랜치를 다결정실리콘층을 메운 후, 상기 다결정실리콘층을 예정된 두께 만큼 열산화시켜 필드 산화막을 형성하였으므로, 다결정실리콘층이 제2질화막에 둘러싸여 있어 버즈빅이 형성되지 않아 소자의 고집적화에 유리하고 소자 동작의 신뢰성이 증가되며, 필드 산화막의 크기의 조절이 가능하며 공정이 간단하여 공정수율을 향상 시킬 수 있다.The present invention relates to a device isolation method for a semiconductor device, wherein a trench is formed by etching a portion of the semiconductor substrate as a device isolation region to a predetermined depth using a first pad oxide film and a first nitride film pattern as a mask, and forming a trench. A first pad oxide film and a second nitride film made of TEOS are formed on the entire surface to a thickness not filling the trench, and the trench is filled with a polysilicon layer, and the polycrystalline silicon layer is thermally oxidized to a predetermined thickness. Since the oxide film is formed, the polysilicon layer is surrounded by the second nitride film so that no buzz is formed, which is advantageous for high integration of the device, the reliability of device operation is increased, the size of the field oxide film is adjustable, and the process yield is simple. Can improve.

Description

반도체소자의 소자분리 방법Device Separation Method of Semiconductor Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1C도는 본 발명에 따른 반도체소자의 소자분리 공정도.1A to 1C are device isolation process diagrams of a semiconductor device according to the present invention.

Claims (8)

반도체기판상에 제1패드산화막을 형성하는 공정과, 상기 제1패드산화막상에 제1질화막을 형성하는 공정과, 상기 반도체기판에서 소자분리영역으로 예정되어 있는 부분 상측의 제1질화막과 제1패드산화막을 순차적으로 제거하여 반도체기판을 노출시키는 제1질화막 및 제2패드산화막 패턴을 형성하는 공정과, 상기 구조의 전표면에 제2패드산화막과 제2질화막을 순차적으로 형성하되 상기 트랜치를 메우지 않는 두께로 형성하는 공정과, 상기 트랜치를 다결정실리콘층을 메우는 공정과, 상기 다결정실리콘층 상측의 예정된 두께를 열산화시켜 필드산화막을 형성하는 공정을 구비하는 반도체소자의 소자분리 방법.Forming a first pad oxide film on the semiconductor substrate, forming a first nitride film on the first pad oxide film, and forming a first nitride film and a first upper portion of the semiconductor substrate as a device isolation region. Removing the pad oxide film sequentially to form a first nitride film and a second pad oxide film pattern exposing the semiconductor substrate; and sequentially forming a second pad oxide film and a second nitride film on the entire surface of the structure, and forming the trench. And forming a field oxide film by thermally oxidizing a predetermined thickness of the polysilicon layer above the trench, and filling the trench with a polysilicon layer. 제1항에 있어서, 상기 트랜치를 1000~20000Å의 깊이로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 방법.The device isolation method of claim 1, wherein the trench is formed to a depth of 1000 to 20000 Å. 제1항에 있어서, 상기 제1 및 제2패드산화막을 300~900Å두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 방법.The method of claim 1, wherein the first and second pad oxide films are formed to have a thickness of about 300 to about 900 μs. 제1항에 있어서, 상기 제1 및 제2질화막을 500~2000Å두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 방법.2. The method of claim 1, wherein the first and second nitride films are formed to a thickness of 500 to 2000 GPa. 제1항에 있어서, 상기 필드 산화막을 2000~5000Å두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 방법.2. The method of claim 1, wherein the field oxide film is formed at a thickness of 2000 to 5000 microns. 제1항에 있어서, 상기 제2패드산화막을 TEOS로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 방법.The method of claim 1, wherein the second pad oxide layer is formed of TEOS. 제1항에 있어서, 상기 열산화를 800~1200℃에서 실시하는 것을 특징으로 하는 반도체소자의 소자분리 방법.The method of claim 1, wherein the thermal oxidation is performed at 800 to 1200 ° C. 3. 제1항에 있어서, 상기 열산화를 TCA를 포함하는 가스 분위기에서 습식산화시키는 것을 특징으로 하는 반도체소자의 소자분리 방법.The method of claim 1, wherein the thermal oxidation is wet oxidation in a gas atmosphere containing TCA. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940039056A 1994-12-29 1994-12-29 Method for forming isolation layer of semiconductor device KR100297171B1 (en)

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KR100297171B1 KR100297171B1 (en) 2001-10-24

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100418435B1 (en) * 2001-12-26 2004-02-14 한국전자통신연구원 Method for fabricating a power integrated circuit device
KR100512167B1 (en) * 2001-03-12 2005-09-02 삼성전자주식회사 Method of forming trench type isolation layer

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100492790B1 (en) * 1997-06-28 2005-08-24 주식회사 하이닉스반도체 Device isolation insulating film formation method of semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960006434B1 (en) * 1992-11-19 1996-05-15 현대전자산업주식회사 Trench isolation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100512167B1 (en) * 2001-03-12 2005-09-02 삼성전자주식회사 Method of forming trench type isolation layer
KR100418435B1 (en) * 2001-12-26 2004-02-14 한국전자통신연구원 Method for fabricating a power integrated circuit device

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