KR970018748A - Method of manufacturing ferroelectric capacitor - Google Patents

Method of manufacturing ferroelectric capacitor Download PDF

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Publication number
KR970018748A
KR970018748A KR1019950032982A KR19950032982A KR970018748A KR 970018748 A KR970018748 A KR 970018748A KR 1019950032982 A KR1019950032982 A KR 1019950032982A KR 19950032982 A KR19950032982 A KR 19950032982A KR 970018748 A KR970018748 A KR 970018748A
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KR
South Korea
Prior art keywords
forming
electrode
interlayer insulating
insulating layer
ferroelectric
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KR1019950032982A
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Korean (ko)
Inventor
강창석
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김광호
삼성전자 주식회사
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950032982A priority Critical patent/KR970018748A/en
Publication of KR970018748A publication Critical patent/KR970018748A/en

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/65Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

강유전체 커패시터의 제조방법에 대해 기재되어 있다. 이는, 반도체기판에 트랜지스터를 형성하는 제1 단계, 트랜지스터가 형성되어 있는 반도체기판 전면에 층간절연층을 형성하는 제2 단계, 트랜지스터의 소오스 및 드레인 영역을 노출시키기 위한 패턴층을 층간절연층 상에 형성하는 제3 단계, 패턴층을 마스크로 하여 층간절연층을 두께 일부를 등방성식각하는 제4 단계, 패턴층을 마스크로 하여 등방성식각 후 남아 있는 층간절연층을 이방성식각함으로써 소오스 및 드레인을 각각 노출시키는 제1 및 제2 홀을 형성하는 제5 단계, 홀들이 형성되어 있는 반도체기판 전면에 제1 전극, 강유전체 및 제2 전극을 차례대로 적층하는 제6 단계, 제1전극, 강유전체 및 제2전극을 패터닝함으로써 제1 홀 내에만 커패시터를 형성하는 제7 단계 및 금속배선을 형성하는 제8 단계를 포함하는 것을 특징으로 한다. 따라서, 셀 정전용량 및 집적도가 종래 보다 큰 강유전체 커패시터를 얻을 수 있다.A method of making a ferroelectric capacitor is described. This includes a first step of forming a transistor on a semiconductor substrate, a second step of forming an interlayer insulating layer on the entire surface of the semiconductor substrate on which the transistor is formed, and a pattern layer for exposing the source and drain regions of the transistor on the interlayer insulating layer. The third step of forming, the fourth step of isotropically etching the interlayer insulating layer with a pattern layer as a mask, the fourth step, anisotropically etching the remaining interlayer insulating layer after the isotropic etching using the pattern layer as a mask to expose the source and drain, respectively A fifth step of forming the first and second holes to be made; a sixth step of sequentially stacking the first electrode, the ferroelectric, and the second electrode on the entire surface of the semiconductor substrate on which the holes are formed; the first electrode, the ferroelectric, and the second electrode And a seventh step of forming a capacitor only in the first hole by patterning and an eighth step of forming a metal wiring. Therefore, a ferroelectric capacitor having a higher cell capacitance and a higher degree of integration can be obtained.

Description

강유전체 커패시터의 제조방법Method of manufacturing ferroelectric capacitor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 일 방법에 의한 강유전체 커패시터의 제조방법을 설명하기 위해 도시한 단면도들이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a ferroelectric capacitor according to one method of the present invention.

Claims (5)

반도체기판에 트랜지스터를 형성하는 제1 단계; 상기 트랜지스터가 형성되어 있는 반도체기판 전면에 층간절연층을 형성하는 제2 단계; 상기 트랜지스터의 소오스 및 드레인 영역을 노출시키기 위한 패턴층을 상기 층간절연층 상에 형성하는 제3 단계; 상기 패턴층을 마스크로 하여 층간절연층 두께 일부를 등방성식각하는 제4 단계; 상기 패턴층을 마스크로 하여 상기 등방성식각 후 남아 있는 층간절연층을 이방성식각함으로써 상기 소오스 및 드레인을 각각 노출시키는 제1 및 제2 홀을 형성하는 제5 단계; 상기 홀들이 형성되어 있는 반도체기판 전면에 제1 전극, 강유전체 및 제2 전극을 차례대로 적층하는 제6 단계; 상기 제1전극, 강유전체 및 제2전극을 패터닝함으로써 상기 제1 홀 내에만 커패시터를 형성하는 제7 단계; 및 금속배선을 형성하는 제8 단계를 포함하는 것을 특징으로 하는 강유전체 커패시터의 제조방법.Forming a transistor on the semiconductor substrate; A second step of forming an interlayer insulating layer on an entire surface of the semiconductor substrate on which the transistor is formed; A third step of forming a pattern layer on the interlayer insulating layer for exposing source and drain regions of the transistor; A fourth step of isotropically etching a part of the interlayer dielectric layer thickness using the pattern layer as a mask; A fifth step of forming first and second holes exposing the source and drain by anisotropically etching the interlayer insulating layer remaining after the isotropic etching using the pattern layer as a mask; A sixth step of sequentially stacking a first electrode, a ferroelectric, and a second electrode on the entire surface of the semiconductor substrate on which the holes are formed; A seventh step of forming a capacitor only in the first hole by patterning the first electrode, ferroelectric, and second electrode; And an eighth step of forming metal wirings. 제1항에 있어서, 상기 제5 단계 후, 상기 제1 및 제2 홀 하부에 텅스텐막을 형성하는 공정을 추가하는 것을 특징으로 하는 강유전체 커패시터의 제조방법.The method of claim 1, further comprising: forming a tungsten film under the first and second holes after the fifth step. 제1항에 있어서, 상기 층간절연층은 보론-인이 도우프된 실리콘 글래스(BPSG), 인이 도우프된 실리콘 글래스(PSG) 및 스핀-온 글래스(SOG) 중 어느 하나로 형성되는 것을 특징으로 하는 강유전체 커패시터의 제조방법.The method of claim 1, wherein the interlayer insulating layer is formed of any one of boron-phosphorus-doped silicon glass (BPSG), phosphorus-doped silicon glass (PSG) and spin-on glass (SOG). Method for producing a ferroelectric capacitor. 제1항에 있어서, 상기 강유전체는 PZT, PbTiO3, BaTiO3, Bi3Ti4012, BST, 및 STO 중 어느 하나인 것을 특징으로 하는 강유전체 커패시터의 제조방법.The method of claim 1, wherein the ferroelectric is any one of PZT, PbTiO3, BaTiO3, Bi3Ti4012, BST, and STO. 제1항에 있어서, 상기 제1 및 제2 전극은 W, Pt, Ru, Ir, RuO2또는 IrO2및 이들의 조합물질로 형성되는 것을 특징으로 하는 강유전체 커패시터의 제조방법.The method of claim 1, wherein the first and second electrodes are formed of W, Pt, Ru, Ir, RuO 2, or IrO 2 and combinations thereof. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950032982A 1995-09-29 1995-09-29 Method of manufacturing ferroelectric capacitor KR970018748A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100602289B1 (en) * 1998-02-16 2006-07-14 지멘스 악티엔게젤샤프트 Circuit with at least one capacitor and process for producing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100602289B1 (en) * 1998-02-16 2006-07-14 지멘스 악티엔게젤샤프트 Circuit with at least one capacitor and process for producing the same

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