KR0135710B1 - Manufacture of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein a first etching barrier layer, a planarization layer, and a second etching barrier layer are instantaneously formed on the entire surface of a structure in which an interlayer dielectric film and a bit line are formed on a semiconductor substrate. After the charge storage electrode contact hole is formed, a first conductive layer pattern filling the second conductive barrier pattern and a second etching barrier side pattern underneath it are formed, and the planarization layer is removed by using the first etching barrier layer as an etch stop layer. And forming a second conductive layer pattern having a predetermined thickness on the entire surface to fill the charge storage electrode contact hole, and the first and second etching barrier layer patterns formed on the remaining first and second etching barrier layer patterns. Since the charge storage electrode formed of the second conductive layer pattern in contact with the first conductive layer pattern is formed, the capacitance of the capacitor can be increased to improve the reliability and process yield of device operation.

Description

Capacitor Manufacturing Method of Semiconductor Device

1a to 1h is a manufacturing process diagram of a capacitor of a semiconductor device according to the present invention.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 interlayer insulating film

3: bit line 4: first etch barrier layer

5: planarization layer 6: second etching barrier layer

7: charge storage electrode contact hole 8: first conductive layer

9: photosensitive film pattern 10: second conductive layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and in particular, a first etching barrier layer, a planarization layer, and a second etching barrier layer are instantaneously formed on the entire surface where an interlayer insulating film and a bit line are formed, and a charge storage electrode After the contact hole is formed, a first conductive layer pattern filling the second conductive barrier layer and a second etching barrier layer pattern thereunder are formed. The planarization layer is removed by using the first etching barrier layer as an etch stop layer, and the first conductive layer pattern is formed. A semiconductor device capable of improving the reliability and fixed yield of device operation by forming a second conductive layer pattern having a predetermined thickness on the lower layer of the layer pattern to form a charge storage electrode having an increased surface area by a double structure to increase capacitance. It relates to a capacitor manufacturing method of.

Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance because the cell size is reduced.

In particular, in the DRAM device including one MOS transistor and a capacitor, word lines and bit lines are orthogonally arranged at regular intervals in a vertical and horizontal direction on a semiconductor substrate, and a storage electrode of a capacitor is formed on a side of the word line. A contact hole is formed in the center of the storage electrode.

At this time, the capacitor is mainly formed of polysilicon as a conductor, and a storage electrode and a plate electrode are formed, and an oxide film, a nitride film, or an oxide-nitride-oxide film, which is a laminated film, is interposed therebetween. Increasing the capacitance of the capacitor, which occupies a large area, reduces the area is an important factor in the high integration of the DRAM device.

Therefore, in order to increase the capacitance (C) of the capacitor which is proportional to the dielectric constant of the dielectric film and the surface area of the capacitor and inversely proportional to the thickness of the dielectric film, a material having a high dielectric constant is used as the dielectric material, or a thin dielectric film is formed or Research is underway to increase the surface area of capacitors.

However, all these methods have their own problems.

In other words, dielectric materials having high dielectric constants, such as Ta ₂ O ₅ , TiO ₂ or SrTiO ₃ , have been studied, but reliability and thin film characteristics such as aggregate breakdown voltage of these materials have not been confirmed. Difficult to apply to a real device, and reducing the thickness of the dielectric film seriously affects the reliability of the capacitor by breaking the dielectric film during device operation.

In addition, in order to increase the surface area of the capacitor, polysilicon is formed in a multi-layer, and then formed through a fin structure or a cylindrical structure that is connected to each other through them, or H. S. G (himi) using a grain of polysilicon. Spherical grain poly silicon (HSG) is used or a combination of these methods. However, these methods also have a problem that the area is reduced due to the high integration of the DRAM and still does not have sufficient capacitance, and the process is complicated.

Although not shown, a conventional semiconductor device looks at a cylindrical capacitor as an example of a capacitor manufacturing method as follows.

First, a device isolation insulating film, a gate oxide film, a gate electrode, a source electrode, a drain electrode, an interlayer insulating film, and a bit line are formed on a semiconductor substrate in a conventional manner, and then a step is formed on the entire surface of the structure. The planarization layer is formed of a material having excellent coating property, and the charge storage electrode contact hole is formed by sequentially removing the planarization layer and the interlayer insulating layer on the source electrode. Thereafter, a first conductive layer filling the charge storage electrode contact hole is formed on an entire surface, and the first conductive layer on the first conductive layer above the charge storage electrode contact hole is removed to fill the charge storage electrode contact hole. After forming the conductive layer pattern, a cylindrical conductive spacer is formed on sidewalls of the sacrificial layer pattern, and the sacrificial layer pattern is removed to form a cylindrical charge storage electrode.

The conventional cylindrical charge storage electrode formed as described above has a small surface area, making it difficult to secure sufficient capacitance, resulting in low reliability of device operation. In order to overcome this problem, a double or triple cylinder is formed, which is complicated in process yield. There is a falling problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a bit line in an interlayer insulating film, and to form a first conductive layer filling a charge storage electrode contact hole, and then forming an upper side and a first side of the bit line. 1 By using an etch barrier layer applied on the lower side of the conductive layer, it is insulated from the second conductive layer applied later to form a charge storage electrode having an increased surface area, thereby increasing capacitance and improving reliability of device operation. This simple to provide a method for manufacturing a capacitor of a semiconductor device that can increase the process yield.

A method of manufacturing a capacitor of a semiconductor device according to the present invention for achieving the above object is to form an interlayer insulating film on a semiconductor substrate on which a device isolation insulating film, a gate oxide film, a gate electrode, a source electrode and a drain electrode are formed. Forming a bit line on the interlayer insulating film, sequentially forming a first visual barrier layer, a planarization layer, and a second etching barrier layer on the entire surface of the structure; Forming a charge storage electrode contact hole by sequentially removing the second etch barrier layer from the second etching barrier layer on the portion intended as the electrode contact to the gate oxide film; and a charge storage electrode mask protecting the second conductive layer portion on the entire surface of the structure. First etching the first conductive layer and the second etching barrier layer sequentially using the first conductive layer pattern filling the charge storage electrode contact hole and Forming a lower second etching barrier layer pattern, forming a second etching barrier layer pattern for removing the planarization layer by using the first etching barrier layer as an etch stop layer, and forming the first etching barrier layer layer. Removing the planarization layer using the etch stop layer, applying the second conductive layer to the entire surface of the structure, and anisotropically etching the second conductive layer to form the lower portion of the first conductive layer pattern. It is to provide a step of forming a second conductive layer pattern remaining only.

Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1A to 1H are capacitor manufacturing plant diagrams of a semiconductor device according to the present invention.

Although not shown, first, lower structures such as a device isolation insulating film, a gate oxide film, a gate electrode, a source electrode, and a drain electrode for device isolation are formed on the semiconductor substrate 1 in a conventional manner. An interlayer insulating film 2 made of an oxide film is formed on the entire surface of the structure, a bit line contact hole for exposing the drain electrode is formed, and a bit line 3 for contacting the drain electrode is formed. Reference)

Then, the first etching barrier layer 4, the planarization layer 5, and the second etching barrier layer 6 of a predetermined material are sequentially formed on the entire surface of the structure. In this case, the first and second etching barrier layers (4) and (6) may be formed of an oxide film, a planarization layer (5), or a material having a relatively large etching selectivity difference from the planarization layer (5). Boro phospho silicate glass (hereinafter referred to as BPSG), phospho silicate glass (hereinafter referred to as PSG), undoped silicate glass (hereinafter referred to as USG), teos ( tetra echylerthosilicate (hereinafter referred to as TEOS) or O ₃ -PSG and the like, and the first and second etching barrier layers 4 and 6 are formed of a nitride film (see also FIG. 1b).

Thereafter, the second etching barrier layer 6 on the source electrode is successively removed from the gate oxide layer to form a charge storage electrode contact hole 7 (see also FIG. 1C).

Then, a first conductive layer 8 made of a silicon layer is formed on the entire surface of the structure to fill the charge storage electrode contact hole 7, and then the first conductive layer filling the charge storage electrode contact hole 7 ( 8) A photosensitive film pattern 9 which is a charge storage electrode mask is formed on the portion (see also FIG. 1d).

Thereafter, the first conductive layer 8 exposed by the photosensitive film pattern 9 is sequentially removed from the first etching barrier layer 6 to fill the charge storage electrode contact hole 7. 8) A pattern and a second etching barrier layer 6 pattern interposed between the planarization layer 5 and the first conductive layer 8 pattern are formed. (See also FIG. 1e.)

Thereafter, a second conductive layer 10 made of a silicon layer is applied to the entire surface of the structure to form a state of FIG. 1g, and then etched entirely without a mask to form sidewalls and lower portions of the first conductive layer 8 pattern. That is, the second conductive layer 10 pattern covering the upper portion of the first etching barrier layer 4 pattern under the first conductive layer 8 pattern and the pillar portion of the exposed first conductive layer 8 pattern. (See also section 1h)

Although not shown, a subsequent process is performed to form a dielectric film and a plate electrode surrounding the surface of the storage electrode to complete the capacitor.

As described above, in the method of manufacturing a capacitor of a semiconductor device according to the present invention, a first etching barrier layer, a planarization layer, and a second etching barrier layer are formed on the entire surface of a structure in which an interlayer insulating film and a bit line are formed on a semiconductor substrate. After sequentially forming a charge storage electrode contact hole, a first conductive layer pattern filling the second conductive barrier layer and a second etching barrier layer pattern thereunder are formed, and the planarization layer is formed using the first etching barrier layer as an etch stop layer. A second conductive layer pattern having a predetermined thickness on the entire surface of the structure to fill the first electrode layer pattern filling the charge storage electrode contact hole, and the remaining first and second etching barrier layer patterns. Since the charge storage electrode is formed to form a second conductive layer pattern formed in contact with the first conductive layer pattern, the capacitance of the capacitor is increased to improve the reliability and process yield of the device operation There is an advantage to this.

Claims (4)

Forming an interlayer insulating film on a semiconductor substrate on which a device isolation insulating film, a gate oxide film, a gate electrode, a source electrode and a drain electrode are formed; forming a bit line on the interlayer insulating film; Sequentially forming the first etching barrier layer, the planarization layer, and the second etching barrier layer, and sequentially removing the second etching barrier layer on the portion of the semiconductor substrate, which is supposed to be a charge storage electrode contact, to the gate oxide layer. Forming a storage electrode contact hole, forming a first conductive layer on the entire surface of the structure to fill the charge storage electrode contact hole, and protecting a portion of the first conductive layer filling the charge storage electrode contact hole. The first conductive layer filling the charge storage cathode contact hole by sequentially etching the first conductive layer and the second etching barrier layer using a charge storage electrode mask. Forming a turn and a second etch barrier layer pattern thereunder; removing the planarization layer using the first etch barrier layer as an etch stop layer; and applying a second conductive layer to the entire surface of the structure. And anisotropically etching the second conductive layer to form a second conductive layer pattern remaining only in a lower portion of the first conductive layer pattern. The method of claim 1, wherein the first and second etching barrier layers are formed of a nitride film. The method of claim 1, wherein the planarization layer is formed of one material selected from the group consisting of an oxide film, BPSG, PSG, USG, TEOS, and O ₃ -PSG. 2. The method of claim 1, wherein the first and second conductive layers are formed of a silicon layer.