KR0135711B1 - Semiconductor memory devcie and its fabrication method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same, wherein an etching barrier is formed of a material having a rectangular protrusion formed on an upper side of a regenerative film formed on an interlayer insulating film and having an etching selectivity difference with the sacrificial film of the protrusion. After forming a spacer and forming a photoresist pattern protecting the peripheral circuit region on the semiconductor substrate, the sacrificial layer covering the peripheral circuit region is removed by removing the sacrificial layer that exposes the etch barrier spacer and the photoresist pattern as a mask. A pattern was formed, and both spacers of the sacrificial layer pattern formed double fence-shaped conductive spacers and dummy spacers surrounding the cell region. Thus, a pillar-shaped conductive layer pattern and a double fence-shaped filled-in electrode contact hole were formed. In the charge preservation electrode composed of spacer, the conductive spacer is double fence Although the structure is formed at the same height, the capacitance is increased, and the dummy spacer is formed between the cell region and the peripheral circuit region, so that the step difference is reduced, thereby increasing the process yield.

Description

Capacitor of semiconductor device and manufacturing method thereof

1 is a layout diagram of a semiconductor device capacitor according to the present invention.

Figure 2a-e is a manufacturing process diagram of a semiconductor device capacitor according to the present invention.

* Explanation of symbols for main parts of the drawings

11 semiconductor substrate 12 field oxide film

13 gate oxide film 14 gate electrode

15 source electrode 16 drain electrode

17: interlayer insulating film 18: charge storage electrode contact hole

19: conductive layer 20: sacrificial film

21: protrusion 22: etching barrier spacer

23, 28: photosensitive film pattern 24: conductive spacer

25: dummy spacer 26: dielectric film

27: conductive layer for plate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, a sacrificial film having a terminal with a protrusion formed on one side is formed on a lower conductive layer filling a charge storage electrode contact hole, and the sidewall of the protrusion is formed of a material having an etching selectivity difference. An etch barrier spacer is formed, and the sacrificial layer is etched using an etch mask to form a sacrificial layer pattern of fence formation, and then a charge preservation electrode is formed on the sidewall of the sacrificial layer pattern as a conductive layer spacer having a constant double-fence structure. Therefore, a semiconductor device capable of increasing capacitance and improving reliability of device operation, and reducing a step difference between a peripheral circuit region and a cell region with a dummy capacitor to improve a process yield provides an individual capacitor and a manufacturing method thereof.

Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size. In a DRAM device consisting of one MOS transistor and a capacitor, a dielectric constant is used to increase the capacitance of the capacitor. Is used as a dielectric material, a thin dielectric film or an increase in the surface area of the charge storage electrode.

However, all these methods have their own problems.

In other words, dielectric materials having high dielectric constants, such as Ta ₂ O ₅ , TiO ₂ or SrTiO ₃ , have been studied, but reliability and thin film characteristics such as junction breakdown voltages of these materials have not been reliably confirmed. Difficult to apply to the device, and reducing the thickness of the dielectric film seriously affects the reliability of the capacitor by breaking the dielectric film during device operation.

Also, in order to increase the surface area of the capacitor, polysilicon may be formed in a multi-layer, and then may be formed in a labyrinth structure having a fin structure, a cylindrical shape or a rectangular frame shape, which penetrate and connect to each other.

In the conventional cylindrical capacitor, after forming a MOS structure on a semiconductor substrate, an interlayer insulating film is formed on the entire surface, and a miter contact hole and a bit line are formed. Then, a material having excellent step coverage on the entire surface, for example, b. blood. s. A planarization layer made of boro phospho silicate glass (hereinafter referred to as BOSG) is sequentially formed to form a charge storage electrode contact groove.

Thereafter, a conductive layer filling the contact hole is formed on the entire surface, and then a thick oxide film pattern, which is a core of a cylindrical capacitor, is formed in a cylindrical shape on the conductive layer above the contact hole, and a cylindrical first conductive layer is formed on the sidewall of the oxide film pattern. Form a spacer.

Next, after forming a conductive layer filling the contact hole on the entire surface, a thick oxide film pattern, which is a core of a cylindrical capacitor, is formed in a cylindrical shape on the conductive layer above the contact hole, and a cylindrical first conductive layer is formed on the sidewall of the oxide film pattern. Form a spacer.

Then, an etch barrier spacer and a second conductive spacer are repeatedly formed on the sidewalls of the first conductive spacer, and the upper conductive layer having the cylindrical shape is patterned on the lower conductive layer to fill the charge storage electrode contact hole. A charge storage electrode comprising a pattern and double cylindrical first and second conductive spacers in contact with the upper side is formed.

The capacitor of the conventional semiconductor device as described above, since the double cylindrical conductive spacers are all formed in a sequential spacer process, as the process proceeds, the height of the conductive spacers decreases, so that capacitance is not constant, and capacitors are formed only in the cell region. Due to the severe step between peripheral circuit areas, disconnection may occur in metal processes and the like, resulting in a decrease in reliability and process yield of device operation.

The present invention is to solve the above problems, an object of the present invention is to etch the sacrificial layer by using an etching barrier spacer formed of a material having a new angle selectivity on the sidewall of the sacrificial layer having a step as a mask of a predetermined shape Fences are formed, conductive spacers are formed on the sidewalls of the fences, and dummy spacers are formed between peripheral circuit areas to reduce the step height, thereby increasing capacitance, thereby improving reliability of device operation and preventing disconnection during metal processing. It is to provide a capacitor of a semiconductor device that can increase the process yield.

Another object of the present invention is to form an etch barrier spacer with a material having an etch selectivity on the sidewall of the stepped sacrificial layer, and to form a fence of the sacrificial layer pattern by etching the sacrificial layer using the etch barrier spacer as a mask Semiconductor that can increase the reliability and process yield of device operation by forming conductive spacer on the side wall of fence, forming double-fence-shaped charge storage electrode, and forming dummy space between cell area and peripheral circuit area The present invention provides a method of manufacturing a capacitor of a device.

The characteristics of the capacitor of the semiconductor device according to the present invention for achieving the above object, the conductive layer pattern filling the charge storage electrode contact hole, and the double-fence shape in which one side is contacted on the conductive layer pattern of the same height A dummy spacer is formed on a boundary portion between a spacer and a cell region on one side of the conductive layer pattern and a peripheral circuit region and surrounds a cell region.

Another feature of the present invention for achieving another object is a step of forming an interlayer insulating film on the entire surface of a semiconductor engine in which a field oxide film, a gate oxide film, a gate electrode, a source and a drain electrode are formed for device isolation; Forming a charge storage electrode contact hole by removing an interlayer insulating film on a predetermined portion of the charge storage electrode contact from an electrode; and applying a conductive layer to an entire surface of the structure to fill the charge storage electrode contact hole; Forming a sacrificial layer on the layer, forming a stepped protrusion having a predetermined shape on the sacrificial film on the portion of the charge storage electrode contact hole spaced apart from the predetermined distance, and etching selection of the sacrificial layer on the sidewall of the protrusion Forming an etch barrier spacer with a non-difference material; Forming a photoresist pattern on the portion of the sacrificial layer, and removing the sacrificial layer exposed by the etch barrier spacer and the photoresist pattern; Forming a sacrificial layer pattern covering the region and removing the etch barrier spacer; forming a spacer with a conductive material on the sidewalls of the sacrificial layer pattern, and forming a double-fence-shaped conductive spacer, a boundary between the peripheral circuit region and the cell region It is to provide a step of forming a dummy spacer surrounding the cell region in the portion.

Hereinafter, the semiconductor device according to the present invention will be described in detail with respect to the capacitor and the manufacturing method thereof.

1 and 2 (a) to (e) are diagrams for explaining a capacitor in a semiconductor device according to the present invention, where FIG. 1 is a layout diagram of a cell region, and FIG. 2 is a manufacturing process diagram. It is an example shown to the boundary of a circuit area, and it demonstrates in association with each other.

First, the field oxide films 12, the gate oxide film 13, and the gate electrode 14 are sequentially formed on the semiconductor engine 11, and the semiconductor engine 11 on both sides of the gate electrode 14 is formed. After forming the source and drain electrodes 15, 16 in the ()), an insulating film (not shown) having a contact hole for exposing the drain electrode 16 is applied, and the bit is in contact with the drain electrode Form a line (not shown). Then, after applying the interlayer insulating film 17 to the entire surface of the structure, the intermediate insulating film 17 on the source electrode 15 is removed to form the charge storage electrode contact hole 18, and the entire surface of the structure The conductive layer 19 is coated on the gap to fill the charge storage electrode contact hole 18.

Thereafter, a sacrificial film 20 is coated on the conductive layer 19 as an insulating material, for example, an oxide film, and a protrusion 21 having a terminal is formed in a predetermined portion of the sacrificial film 20. In this case, as shown in FIG. 1, the protrusion 21 is formed in a square shape extending from an upper side of the charge storage electrode contact hole 18 and a predetermined distance apart from the upper side of the drain electrode 16. See Figure 2 (a).

Next, the etch barrier spacer 22 is formed on a sidewall of the protrusion 21 of the sacrificial layer 20 by using a material having an etching selectivity difference with the sacrificial layer 21, for example, a nitride layer, polycrystalline, or amorphous silicon. Subsequently, a photosensitive film pattern 23 is formed to form the peripheral circuit region state dummy spacer on one side of the sacrificial film 20 (see FIGS. 1 and 2 (b)).

Thereafter, the sacrificial layer 20 and the conductive layer 19 exposed by the photoresist pattern 23 and the etch barrier spacer 22 are sequentially removed to fill the pillars for filling the charge storage electrode contact holes 18. After the sacrificial film 20 pattern is formed in a layer 19 pattern and a rectangular frame in which one side of the conductive layer 19 pattern overlaps, the photoresist pattern 23 and the etch barrier spacer 22 are removed. . The conductive layer 19 may be patterned later without being etched. Then, a conductive layer, for example, a polycrystalline or amorphous silicon layer is applied to the sidewalls of the sacrificial film 20 pattern on the rectangular frame to a predetermined thickness. Anisotropically etch the entire surface to form a double-fence conductive spacer 24. In this case, a dummy spacer 25 is formed on sidewalls of the sacrificial layer 20 pattern remaining at the cell region boundary and surrounded by the cell region, so that the double-fence conductive spacer 24 and the dummy spacer 25 once. It is formed by the process of and has the same height (see FIGS. 1 and 2 (c)).

After that, the sacrificial layer 20 patterns are removed, and the dielectric layer 26 and the conductive layer 27 for the plate electrode are coated on the entire surface of the structure. Next, a photoresist pattern 28 for a plate electrode mask is formed on the plate electrode conductive layer 27 on the cell region. At this time, the dummy spacer 25 is also protected (see FIG. 2 (d)).

Then, the interlayer insulating film 17 is exposed by sequentially removing the plate-electrode conductive layer 27 on the peripheral circuit region exposed by the photosensitive film panner 28 to the charge preserving electrode-conductive layer 19. A charge composed of a columnar conductive layer 19 pattern filling the charge storage electrode contact hole 18 and a double-fence-shaped conductive spacer 24 overlapping one side of the conductive layer 19 pattern. After forming a capacitor including a storage electrode and a dummy spacer 25 surrounding the cell region at the boundary between the cell region and the peripheral circuit region, the photoresist pattern 28 is removed. In this case, the dummy spacer 25 may not be connected to other parts, may be grounded, or may be connected to a plate electrode (see FIG. 2E).

As described above, in the capacitor and the method of manufacturing the semiconductor device according to the present invention, a rectangular protrusion is formed on the side of the sacrificial film formed on the interlayer insulating film, and the etching selectivity difference with the sacrificial film is formed on the sidewall of the protrusion. Forming an etch barrier spacer made of a material, and forming a photoresist pattern protecting the peripheral circuit region in a semiconductor engine, and then forming the etch barrier spacer and the photoresist pattern, and having double fence shapes on both sidewalls of the sacrificial layer pattern. Since the spacers are formed to surround the conductive spacers and the cell region, the conductive spacers have a double fence structure in the charge storage electrodes including a pillar-shaped conductive layer pattern filling the charge storage electrode contact holes and a double fence-shaped conductive spacer. Capacitance increases due to the same height, cell area and peripheral circuit area Since a dummy spacer is formed therebetween, there is an advantage that the process yield is increased because the step is reduced.

Claims (6)

A conductive layer pattern filled with a charge storage electrode contact hole, a conductive spacer having the same height in a double-fence shape in which one side contacts the conductive layer pattern, a cell region on one side of the conductive layer pattern, and a peripheral portion of a peripheral circuit region. A capacitor of a semiconductor device having a dummy spacer formed of a conductive material surrounding the cell region. The capacitor of claim 1, wherein the dummy spacer is any one of those which are not connected to another wiring, connected to a plate electrode, or connected to a ground line. Forming an interlayer insulating film on the entire surface of a semiconductor engine in which a field oxide film, a gate oxide film, a gate electrode, a source electrode and a drain electrode are formed for device isolation, and an interlayer insulating film on a portion of the source electrode which is intended to be a charge storage electrode contact. Removing the charge storage electrode contact hole by removing the charge storage electrode contact hole; applying a conductive layer to the entire surface of the structure to fill the charge storage electrode contact hole; forming a sacrificial layer on the conductive layer; Forming a stepped protrusion having a predetermined shape on the sacrificial film on a portion of the contact hole that is raised and spaced apart from the predetermined distance; forming an etch barrier spacer on a sidewall of the protrusion having an etching selectivity difference between the sacrificial film; Forming a photoresist pattern on the sacrificial film on a portion of the semiconductor engine that is intended to be a peripheral circuit region; Removing the sacrificial layer exposed by the etching barrier spacer and the photosensitive pattern to form a sacrificial layer pattern in which one side contacts the conductive layer filling the charge storage electrode contact hole; and a sidewall of the sacrificial layer patterns as a conductive material. And forming a spacer to form a double-fence conductive spacer having the same height and a dummy spacer surrounding the cell region at the boundary between the peripheral circuit region and the cell region. 4. The method of claim 3, wherein the conductive layer, the conductive spacer, and the dummy spacer are formed of polycrystalline silicon or amorphous silicon. The method of manufacturing a capacitor of a semiconductor device according to claim 3, wherein said sacrificial film is formed of an oxide film. 4. The method of claim 3, wherein the etch barrier spacer is formed of one material arbitrarily selected from the group consisting of a nitride film, polycrystalline silicon, and an amorphous silicon layer.