KR970018096A - Method for forming contact plug of semiconductor device - Google Patents

Method for forming contact plug of semiconductor device Download PDF

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Publication number
KR970018096A
KR970018096A KR1019950029307A KR19950029307A KR970018096A KR 970018096 A KR970018096 A KR 970018096A KR 1019950029307 A KR1019950029307 A KR 1019950029307A KR 19950029307 A KR19950029307 A KR 19950029307A KR 970018096 A KR970018096 A KR 970018096A
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KR
South Korea
Prior art keywords
forming
polysilicon
doped polysilicon
contact plug
insulating film
Prior art date
Application number
KR1019950029307A
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Korean (ko)
Inventor
양원석
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950029307A priority Critical patent/KR970018096A/en
Publication of KR970018096A publication Critical patent/KR970018096A/en

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Abstract

반도체 장치의 도전층간의 상호접속을 위한 콘택 플러그 형성방법을 개시한다. 반도체 장치의 콘택 플러그 형성방법에 있어서, 하부 구조물이 형성된 반도체 기판상에 층간 절연막을 형성하는 단계; 상기 층간 절연막에 콘택 홀을 형성하는 단계; 상기 콘택 홀을 도핑된 폴리실리콘으로 채워서(filling) 콘택 플러그를 형성하는 단계; 상기 콘택 플러그된 도핑된 폴리 실리콘에 소정의 에너지로 불순물을 이온주입을 하는 단계; 상기 도핑된 폴리 실리콘에 이온 주입된 불순물과 폴리 실리콘이 결합하여 새로운 층을 형성하는 단계; 및 상기 층간 절연막과 새로이 결합된 층을 에치 저지대층으로 하여 도핑된 폴리 실리콘의 상부를 제거하는 것을 특징으로 하는 반도체 장치의 제조 방법을 제공한다.A method for forming a contact plug for interconnection between conductive layers of a semiconductor device is disclosed. A method of forming a contact plug in a semiconductor device, the method comprising: forming an interlayer insulating film on a semiconductor substrate on which a lower structure is formed; Forming a contact hole in the interlayer insulating film; Filling the contact hole with doped polysilicon to form a contact plug; Implanting impurities into the contact plugged doped polysilicon with a predetermined energy; Combining the doped polysilicon with ion implanted impurities and polysilicon to form a new layer; And removing the upper portion of the doped polysilicon by using a newly bonded layer as the etch stopper layer.

본 발명에 의하면, 폴리 실리콘과 층간절연막 새로이 결합된 층과의 선택비를 수십대 : 1로 유지할 수 있다. 따라서 충분한 식각을 통하여 콘택 플러그를 제외한 모든곳에 도핑된 폴리 실리콘을 제거할 수 있다.According to the present invention, the selectivity ratio between polysilicon and the newly interlayered insulating film can be maintained at several tens: one. Therefore, sufficient etching can remove polysilicon doped everywhere except the contact plug.

Description

반도체 장치의 콘택 플러그 형성방법Method for forming contact plug of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 콘택 플러그 형성 방법을 공정 순서대로 나타낸 단면도들이다.2 is a cross-sectional view showing the contact plug forming method according to the present invention in the order of process.

Claims (4)

반도체 장치의 콘택 플러그 형성방법에 있어서, 하부 구조물이 형성된 반도체 기판상에 층간 절연막을 형성하는 단계; 상기 층간 절연막에 콘택홀을 형성하는 단계; 상기 콘택홀을 도핑된 폴리 실리콘으로 채워서(filling) 콘택 플러그를 형성하는 단계; 상기 콘택 플러그된 도핑된 폴리 실리콘에 소정의 에너지로 불순물을 이온주입을 하는 단계; 상기 도핑된 폴리 실리콘에 이온 주입된 불순물과 폴리 실리콘이 결합하여 새로운 층을 형성하는 단계; 및 상기 층간 절연막과 새로이 결합된 층을 에치 저지대층으로 하여 도핑된 폴리 실리콘의 상부를 제거하는 것을 특징으로 하는 반도체 장치의 제조 방법.A method of forming a contact plug in a semiconductor device, the method comprising: forming an interlayer insulating film on a semiconductor substrate on which a lower structure is formed; Forming a contact hole in the interlayer insulating film; Filling the contact hole with doped polysilicon to form a contact plug; Implanting impurities into the contact plugged doped polysilicon with a predetermined energy; Combining the doped polysilicon with ion implanted impurities and polysilicon to form a new layer; And removing the upper portion of the doped polysilicon using the newly bonded layer as the etch stopper layer. 제1항에 있어서, 상기 이온주입된 불순물은 O2및 N2중 어느 하나를 사용하는 것을 특징으로 하는 반도체 장치의 제조 방법.The method of claim 1, wherein the ion implanted impurity uses any one of O 2 and N 2 . 제1항에 있어서, 상기 새로운 층은 산화층 및 질화층 중 어느 하나로 형성되는 것을 특징으로 하는 반도체 장치의 제조 방법.The method of claim 1, wherein the new layer is formed of any one of an oxide layer and a nitride layer. 제1항에 있어서, 상기 도핑된 폴리 실리콘의 상부을 제거함에 있어서 등방성 식각을 이용하는 것을 특징으로 하는 반도체 장치의 제조 방법.The method of claim 1, wherein isotropic etching is used to remove the upper portion of the doped polysilicon. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950029307A 1995-09-07 1995-09-07 Method for forming contact plug of semiconductor device KR970018096A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950029307A KR970018096A (en) 1995-09-07 1995-09-07 Method for forming contact plug of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950029307A KR970018096A (en) 1995-09-07 1995-09-07 Method for forming contact plug of semiconductor device

Publications (1)

Publication Number Publication Date
KR970018096A true KR970018096A (en) 1997-04-30

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Application Number Title Priority Date Filing Date
KR1019950029307A KR970018096A (en) 1995-09-07 1995-09-07 Method for forming contact plug of semiconductor device

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KR (1) KR970018096A (en)

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