KR970018020A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970018020A
KR970018020A KR1019960037853A KR19960037853A KR970018020A KR 970018020 A KR970018020 A KR 970018020A KR 1019960037853 A KR1019960037853 A KR 1019960037853A KR 19960037853 A KR19960037853 A KR 19960037853A KR 970018020 A KR970018020 A KR 970018020A
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KR
South Korea
Prior art keywords
diffusion layer
type diffusion
semiconductor substrate
type
manufacturing
Prior art date
Application number
KR1019960037853A
Other languages
Korean (ko)
Inventor
리스틱 류비사
에이. 2세 셔만스카이 프랭크
시게루 미즈노
마나부 다가미
다카노리 요시무라
아쯔시 오구라
요이찌로 누마사와
아끼라 도이
마사야스 단죠
토마스 마틴 헨리
쥰 스에나가
Original Assignee
빈센트 비 인그라시아
모토로라 인코포레이티드
니시히라 순지
아네루바 가부시기가이샤
가네꼬 히사시
닛뽕덴끼 가부시끼가이샤
야스이 데이조오
닛신덴끼 가부시끼가이샤
헨넬리 헬렌 에프
엠이엠씨 일렉트로닉 머티어리얼즈 인코포레이티드
이데이 노부유키
소니 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/523,581 external-priority patent/US5550090A/en
Priority claimed from JP7257162A external-priority patent/JPH0982812A/en
Priority claimed from JP26483395A external-priority patent/JP3585606B2/en
Priority claimed from US08/530,612 external-priority patent/US5908504A/en
Priority claimed from JP07245636A external-priority patent/JP3080867B2/en
Application filed by 빈센트 비 인그라시아, 모토로라 인코포레이티드, 니시히라 순지, 아네루바 가부시기가이샤, 가네꼬 히사시, 닛뽕덴끼 가부시끼가이샤, 야스이 데이조오, 닛신덴끼 가부시끼가이샤, 헨넬리 헬렌 에프, 엠이엠씨 일렉트로닉 머티어리얼즈 인코포레이티드, 이데이 노부유키, 소니 가부시기가이샤 filed Critical 빈센트 비 인그라시아
Publication of KR970018020A publication Critical patent/KR970018020A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides

Abstract

시트저항이 낮은 N형 확산층 및 P형 확산층을 가지고 또한 신뢰성도 높은 반도체장치를 제조한다.A semiconductor device having an N type diffusion layer and a P type diffusion layer having a low sheet resistance and high reliability is manufactured.

Si기판(31)의 표면을 노출시킨 상태에서 As+(45)를 이온주입하여 N+형의 확산층(46)을 형성하고, Si기판(31)을 SiO2막으로 피복한 상태에서 BF2 +를 이온주입하여 P+형의 확산층을 형성한다. 이 결과, N+형의 확산층(46) 및 P+형의 확산층의 표면에 있어서의 실리사이드화 반응을 촉진시킬 수 있다. 또, 실리사이드화 반응시에 N+형의 확산층(46)에 있어서의 알로이스파이크를 방지할 수 있고, P+형의 확산층에서는 단(短)채널효과를 억제할 수 있다.As + (45) is ion-implanted with the surface of the Si substrate 31 exposed to form an N + type diffusion layer 46, and the Si substrate 31 is covered with SiO 2 film and BF 2 +. Ion implantation to form a P + type diffusion layer. As a result, the silicided reaction in the surface of the N <+> type diffusion layer 46 and the P <+> type diffusion layer can be accelerated | stimulated. In the silicided reaction, alloy spikes in the N + type diffusion layer 46 can be prevented, and the short channel effect can be suppressed in the P + type diffusion layer.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 제1도에 계속되는 공정을 순차로 나타낸 측단면도.2 is a side cross-sectional view sequentially illustrating a process following FIG. 1.

Claims (4)

반도체기판에 N형 확산층과 P형 확산층을 가지고, 상기 N형 확산층 및 상기 P형 확산층의 표면에 반도체와 금속과의 화합물막을 가지는 반도체장치의 제조방법에 있어서, 상기 반도체기판의 표면을 노출시킨 상태에서 이 반도체기판에 N형 불순물을 이온주입하여 상기 N형 확산층을 형성하는 공정과, 상기 반도체기판의 표면을 피복막으로 피복한 상태에서 이 피복막을 통하여 상기 반도체기판에 P형 불순물을 이온주입하여 상기 P형 확산층을 형성하는 공정과, 상기 N형 불순물 및 상기 P형 불순물의 상기 이온주입 후에, 상기 N형 확산층 및 상기 P형 확산층의 표면에 상기 화합물막을 형성하는 공정을 구비하는 것을 특징으로 하는 반도체장치의 제조방법.A semiconductor device manufacturing method comprising a semiconductor substrate having an N-type diffusion layer and a P-type diffusion layer, and having a compound film of a semiconductor and a metal on the surfaces of the N-type diffusion layer and the P-type diffusion layer, wherein the surface of the semiconductor substrate is exposed. Forming an N-type diffusion layer by ion implanting N-type impurities into the semiconductor substrate, and ion-implanting P-type impurities into the semiconductor substrate through the coating film while the surface of the semiconductor substrate is covered with a coating film. Forming the P-type diffusion layer and forming the compound film on the surfaces of the N-type diffusion layer and the P-type diffusion layer after the ion implantation of the N-type impurity and the P-type impurity. Method of manufacturing a semiconductor device. 청구항 제1에 있어서, 상기 N형 불순물로서 As를 사용하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein As is used as the N-type impurity. 청구항 제1에 있어서, 상기 픽복막으로서 SiO2막을 사용하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein an SiO 2 film is used as the picking film. 청구항 제3에 있어서, 상기 반도체기판의 표면을 상기 SiO2막으로 피복한 상태에서, 상기 반도체기판에 이온주입한 상기 N형 불순물 및 상기 P형 불순물을 활성화시키기 위한 열처리를 행하는 것을 특징으로 하는 반도체장치의 제조방법.The semiconductor according to claim 3, wherein the semiconductor substrate is subjected to a heat treatment for activating the N-type impurities and the P-type impurities which are ion-implanted into the semiconductor substrate while the surface of the semiconductor substrate is covered with the SiO 2 film. Method of manufacturing the device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960037853A 1995-09-05 1996-09-02 Manufacturing Method of Semiconductor Device KR970018020A (en)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US523,581 1995-09-05
US08/523,581 US5550090A (en) 1995-09-05 1995-09-05 Method for fabricating a monolithic semiconductor device with integrated surface micromachined structures
JP95-257162 1995-09-08
JP7257162A JPH0982812A (en) 1995-09-08 1995-09-08 Manufacture of semiconductor device
JP95-264833 1995-09-19
JP26483395A JP3585606B2 (en) 1995-09-19 1995-09-19 Electrode device of CVD equipment
US08/530,612 US5908504A (en) 1995-09-20 1995-09-20 Method for tuning barrel reactor purge system
US08/530,612 1995-09-20
JP07245636A JP3080867B2 (en) 1995-09-25 1995-09-25 Method for manufacturing SOI substrate
JP95-245636 1995-09-25

Publications (1)

Publication Number Publication Date
KR970018020A true KR970018020A (en) 1997-04-30

Family

ID=66321858

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960037853A KR970018020A (en) 1995-09-05 1996-09-02 Manufacturing Method of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR970018020A (en)

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