KR970017591A

KR970017591A - Back bias voltage control method of semiconductor memory device

Info

Publication number: KR970017591A
Application number: KR1019950029582A
Authority: KR
Inventors: 이상재
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-09-11
Filing date: 1995-09-11
Publication date: 1997-04-30

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 반도체 메모리장치의 백 바이어스 발생회로에 관한 것이다.The present invention relates to a back bias generation circuit of a semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래방법을 사용하는 경우, 동작전류가 커지게 되어 전류소비가 커진다. 이는 저전력소비를 수구하는 반도체 메모리장치의 발전에 장애요소가 된다.In the case of using the conventional method, the operating current becomes large and the current consumption becomes large. This is an obstacle to the development of semiconductor memory devices that consume low power.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

출력되는 백 바이어스전압을 감지하기 위한 디텍터와, 상기 디텍터의 출력에 응답하여 주기적인 구형파를 출력하는 오실레이터와, 상기 오실레이터의 출력에 응답하여 음전압레벨의 백 바이어스전압을 출력하는 펌핑수단을 구비하는 반도체 메모리장치의 백 바이어스전압 제어방법에 있어서, 리프레시신호에 응답하여 소정의 펄스를 발생하는 펄스발생수단과, 전원전압단자와 소정외 제1감지노드사이에 접속되고 제어전극에 접지전압단자가 접속된 제1트랜지스터와, 상기 제1감지노드와 접지전압단자사이에 채널이 접속되고 제어전극에 상기 펄스발생 수단의 출력단이 접속된 제2전류패스와, 상기 제1감지노드에 입력단이 접속되고 소정의 제2노드에 출력단이 접속된 제1인버터와, 상기 제1감지노드와 접지전압단자시이에 접속되고 제어전극에 상기 제2감지노드가 접속되며 상기 제1전류패스수단과 병렬접속된 제2전류패스수단과, 상기 제2감지노드에 입력단이 접속된 구동인버터로 구성된 모드선택회로의 제1트랜지스터와 상기 제1감지노드사이에 휴즈수단을 더 구비하여 상기 제1감지노드의 전압을 가변적으로 출력하므로써 상기 오실레이터의 주기를 상기 모드선택회로의 출력신호에 의해 제어되는 백바이어스 발생회로를 구비하므로써 동작전류를 줄일 수 있게 되었다.A detector for sensing an output back bias voltage, an oscillator for outputting a periodic square wave in response to the output of the detector, and pumping means for outputting a back bias voltage of a negative voltage level in response to the output of the oscillator; A method of controlling a back bias voltage of a semiconductor memory device, comprising: a pulse generating means for generating a predetermined pulse in response to a refresh signal, a power supply terminal, and a predetermined first sensing node, and a ground voltage terminal connected to a control electrode; A second current path having a first transistor connected thereto, a channel connected between the first sensing node and a ground voltage terminal, an output terminal of the pulse generating means connected to a control electrode, and an input terminal connected to the first sensing node, A first inverter having an output terminal connected to a second node of the first inverter, a first sensing node and a ground voltage terminal, A first transistor of the mode selection circuit comprising a second current path means connected to a second sensing node and connected in parallel with the first current path means, and a drive inverter connected to an input terminal of the second sensing node; By further comprising a fuse means between the nodes to variably output the voltage of the first sensing node to reduce the operating current by having a back bias generation circuit controlled by the output signal of the mode selection circuit to the cycle of the oscillator It became.

4. 발명의 중요한 용도4. Important uses of the invention

저전류소비용 반도체 메모리장치.Low current consumption semiconductor memory device.

Description

Back bias voltage control method of semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명의 실시예에 따른 백 바이어스 발생회로의 블럭도,5 is a block diagram of a back bias generation circuit according to an embodiment of the present invention;

제6도는 본 발명의 실시예에 따른 오실레이터의 회로도,6 is a circuit diagram of an oscillator according to an embodiment of the present invention;

제7도는 본 발명의 실시예에 따른 모드선택회로의 회로도,7 is a circuit diagram of a mode selection circuit according to an embodiment of the present invention;

제8도는 본 발명의 실시예에 따른 펌핑전압 발생회로의 블럭도.8 is a block diagram of a pumping voltage generating circuit according to an embodiment of the present invention.

Claims

A detector that feedbacks a back bias voltage to a predetermined target level, detects and compares a predetermined target level, an oscillator that outputs a square wave oscillation signal in response to an output of the detector, and a period of an oscillation signal output from the oscillator A method of controlling a back bias voltage of a semiconductor memory device according to the present invention, comprising a pumping circuit for pumping charge of a substrate and outputting a back bias voltage having a predetermined negative voltage level, the method comprising: generating a predetermined pulse in response to a refresh signal; A first transistor connected between a pulse generating means, a power supply voltage terminal and a predetermined first sensing node, and a ground voltage terminal connected to a control electrode, and a channel connected to the first sensing node and a ground voltage terminal, A second current path having an output terminal of the pulse generating means connected thereto, and an input terminal connected to the first sensing node A second current connected between a first inverter having an output terminal connected to a second node, the first sensing node and a ground voltage terminal, and a second sensing node connected to a control electrode and connected in parallel with the first current path means; A fuse means is further provided between the first transistor and the first transistor of the mode selection circuit including a pass means and a drive inverter having an input terminal connected to the second sensing node to variably output the entire arm of the first sensing node. And controlling a period of the oscillator by an output signal of the mode selection circuit.

The method of claim 1, wherein the first current path means is an enMOS transistor.

3. The method of claim 1 or 2, wherein the first current path means determines a channel width by the refresh signal.

※ Note: The disclosure is based on the initial application.