KR970016964A - Address Transition Detection Circuit Using Pulse Width Delay Circuit - Google Patents

Address Transition Detection Circuit Using Pulse Width Delay Circuit Download PDF

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Publication number
KR970016964A
KR970016964A KR1019950030100A KR19950030100A KR970016964A KR 970016964 A KR970016964 A KR 970016964A KR 1019950030100 A KR1019950030100 A KR 1019950030100A KR 19950030100 A KR19950030100 A KR 19950030100A KR 970016964 A KR970016964 A KR 970016964A
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KR
South Korea
Prior art keywords
pulse width
address transition
semiconductor memory
control signal
detection circuit
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Application number
KR1019950030100A
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Korean (ko)
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KR0177743B1 (en
Inventor
이강훈
류영균
이형모
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김광호
삼성전자 주식회사
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Priority to KR1019950030100A priority Critical patent/KR0177743B1/en
Publication of KR970016964A publication Critical patent/KR970016964A/en
Application granted granted Critical
Publication of KR0177743B1 publication Critical patent/KR0177743B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

불휘발성 반도체 메모리 장치에 적합한 펄스폭 지연회로를 사용한 어드레스 천이 검출 회로.An address transition detection circuit using a pulse width delay circuit suitable for a nonvolatile semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

센스앰프의 데이타 센싱동작을 안정하게 보장할 수 있는 반도체 메모리의 어드레스 천이 검출 회로를 제공함에 있다.An address transition detection circuit of a semiconductor memory capable of stably guaranteeing a data sensing operation of a sense amplifier is provided.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

펄스폭 지연부를 포함하는 어드레스 천이 검출 회로를 가지는 반도체 메모리 장치에 있어서, 외부 전원전압의 이상 레벨에 응답하는 검출 제어신호를 발생하는 모니터링 수단과, 상기 검출 제어신호에 응답하여 상기 펄스폭 지연부로부터 출력되는 센스앰프 제어신호의 펄스폭을 확장하는 펄스폭 확장수단을 가짐을 특징으로 한다.A semiconductor memory device having an address transition detection circuit including a pulse width delay unit, comprising: monitoring means for generating a detection control signal in response to an abnormal level of an external power supply voltage; and from the pulse width delay unit in response to the detection control signal. And a pulse width extending means for extending the pulse width of the sense amplifier control signal to be output.

4. 발명의 중요한 용도4. Important uses of the invention

센스앰프의 데이타 센싱동작을 안정하게 보장하는 반도체 메모리의 어드레스 천이 검출 회로에 사용된다.The semiconductor memory device is used in an address transition detection circuit of a semiconductor memory which stably guarantees a data sensing operation of a sense amplifier.

Description

펄스폭 지연회로를 사용한 어드레스 천이 검출 회로Address Transition Detection Circuit Using Pulse Width Delay Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 반도체 메모리 소자의 블럭도.4 is a block diagram of a semiconductor memory device of the present invention.

제5도는 본 발명의 펄스폭 지연 회로도.5 is a pulse width delay circuit diagram of the present invention.

Claims (5)

펄스폭 지연부를 포함하는 어드레스 천이 검출 회로를 가지는 반도체 메모리 장치에 있어서, 외부 전원전압의 이상 레벨에 응답하는 검출 제어신호를 발생하는 모니터링 수단과, 상기 검출 제어신호에 응답하여 상기 펄스폭 지연부로부터 출력되는 센스앰프 제어신호의 펄스폭을 확장하는 펄스폭 확장수단을 가짐을 특징으로 하는 어드레스 천이 검출 회로.A semiconductor memory device having an address transition detection circuit including a pulse width delay unit, comprising: monitoring means for generating a detection control signal in response to an abnormal level of an external power supply voltage; and from the pulse width delay unit in response to the detection control signal. And a pulse width extending means for extending a pulse width of an output sense amplifier control signal. 제1항에 있어서, 상기 모니터링 수단은 상기 외부 전원전압을 수신하여 그의 레벨을 인버딩하는 제1인버터와, 상기 제1인버터의 출력단에 게이트가 연결된 제1엔형 및 피형 모오스 트랜지스터와, 상기 제1엔형 트랜지스터의 드레인에 소오스가 연결된 디플리션 타입 엔 모오스 트랜지스터와, 상기 디플리션 타입 엔 모오스 트랜지스터와 상기 전원전압간에 채널이 연결된 제2피형 모오스 트랜지스터와, 상기 제1피형 트랜지스터의 드레인에 차례로 연결된 릴레이 소자를 포함함을 특징으로 하는 어드레스 천이 검출 회로.The display device of claim 1, wherein the monitoring means comprises: a first inverter receiving the external power supply voltage and inverting a level thereof, a first N-type and a P-type MOS transistor having a gate connected to an output terminal of the first inverter, A depletion type NMOS transistor whose source is connected to the drain of the N-type transistor, a second PMOS transistor whose channel is connected between the depletion type NMOS transistor and the power supply voltage, and a drain of the first PMOS transistor An address transition detection circuit comprising a relay element. 제1항 또는 제2항에 있어서, 상기 펄스폭 확장수단은 캐패시터, 인버터들과, 상기 펄스폭 지연부에 연결된 전송 게이트를 포함하는 것을 특징으로 하는 어드레스 천이 검출 회로.3. The address transition detection circuit according to claim 1 or 2, wherein the pulse width extension means includes a capacitor, inverters, and a transfer gate connected to the pulse width delay portion. 어드레스 천이 감지회로를 사용하는 반도체 메모리 소자와, ATD회로의 출력 신호가 센스앰프를 제어하는 반도체 메모리 소자에 있어서, 외부에서 인가하는 전원 전압의 레벨을 감지하여 전원 전압 레벨 감지 회로의 출력이 펄스폭 지연 회로의 펄스폭을 제어하여 센스앰프 제어 신호의 펄스폭이 변하도록 하는 수단을 가지는 반도체 메모리.A semiconductor memory device using an address transition detection circuit and a semiconductor memory device in which an output signal from an ATD circuit controls a sense amplifier. And a means for controlling the pulse width of the delay circuit so that the pulse width of the sense amplifier control signal is changed. 제4항에 있어서, 상기 전원 전압 레벨 감지회로의 출력이 펄스폭 지연 회로내의 캐패시터의 연결 여부를 제어하여 상기 펄스폭 지연 회로의 펄스폭을 제어하여 센스앰프 제어신호의 펄스폭이 변하도록 하는 것을 특징으로 하는 반도체 메모리.5. The method of claim 4, wherein the output of the power supply voltage level sensing circuit controls whether a capacitor in the pulse width delay circuit is connected to control the pulse width of the pulse width delay circuit so that the pulse width of the sense amplifier control signal is changed. A semiconductor memory characterized by the above-mentioned. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950030100A 1995-09-14 1995-09-14 Address transition circuit KR0177743B1 (en)

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KR1019950030100A KR0177743B1 (en) 1995-09-14 1995-09-14 Address transition circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950030100A KR0177743B1 (en) 1995-09-14 1995-09-14 Address transition circuit

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KR970016964A true KR970016964A (en) 1997-04-28
KR0177743B1 KR0177743B1 (en) 1999-05-15

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KR100760153B1 (en) * 2001-05-21 2007-09-18 매그나칩 반도체 유한회사 Voltage adapted two-phase clock generating circuits

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