KR970049242A - Clock Enable Buffer of Synchronous DRAM - Google Patents

Clock Enable Buffer of Synchronous DRAM Download PDF

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Publication number
KR970049242A
KR970049242A KR1019950051493A KR19950051493A KR970049242A KR 970049242 A KR970049242 A KR 970049242A KR 1019950051493 A KR1019950051493 A KR 1019950051493A KR 19950051493 A KR19950051493 A KR 19950051493A KR 970049242 A KR970049242 A KR 970049242A
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KR
South Korea
Prior art keywords
buffer
signal
clock enable
current
transistors
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Application number
KR1019950051493A
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Korean (ko)
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KR0154662B1 (en
Inventor
한진만
이정배
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김광호
삼성전자 주식회사
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Priority to KR1019950051493A priority Critical patent/KR0154662B1/en
Publication of KR970049242A publication Critical patent/KR970049242A/en
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Publication of KR0154662B1 publication Critical patent/KR0154662B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)

Abstract

본 발명은 클럭을 사용하는 반도체 메모리 장치에서 외부 클럭의 입력을 제어하는 클럭 인에이블 신호(CKE)의 버퍼단에 흐르는 전류량을 별도의 버퍼를 추가하지 않고서도 모드에 따라 제어하는 기능을 갖는 클럭 인에이블 버퍼로서, 차동 증폭기 형의 입력 버퍼 회로(10)와, 서로 상이한 전류 구동력을 갖는 2개의 NMOS 트랜지스터들(MN3,MN4)로 이루어지고 입력 버퍼 회로(10)로 전류를 공급하기 위한 전류 공급 회로(20)와, 셀프 리프레시 신호(PSELF)와 '파워 업(power-up)'의 완료를 나타내는 파워 업 신호(PVCCH)에 응답하여 전류 공급 회로(20)의 전류 공급량을 조절하는 제어 회로(30)로 구성된다.The present invention provides a clock enable having a function of controlling a current amount flowing through a buffer terminal of a clock enable signal CKE that controls an input of an external clock in a semiconductor memory device using a clock according to a mode without adding a separate buffer. As a buffer, a current supply circuit for supplying current to the input buffer circuit 10, comprising an input buffer circuit 10 of a differential amplifier type and two NMOS transistors MN3 and MN4 having different current driving forces from each other ( 20) and a control circuit 30 for adjusting the current supply amount of the current supply circuit 20 in response to the self refresh signal PSELF and the power up signal PVCCH indicating completion of the 'power-up'. It consists of.

Description

동기형 디램의 클럭 인에이블 버퍼Clock Enable Buffer of Synchronous DRAM

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 클럭 인에이블 버퍼의 개략도.2 is a schematic diagram of a clock enable buffer in accordance with the present invention.

제3도는 본 발명에 따른 클럭 인에이블 버퍼의 제1실시예.3 is a first embodiment of a clock enable buffer according to the present invention.

제4도는 본 발명에 따른 클럭 인에이블 버퍼의 제2실시예.4 is a second embodiment of a clock enable buffer according to the present invention.

Claims (4)

소정의 기준 전압 신호와 외부 클럭 인에이블 신호가 입력되는 것에 응답하여 내부 클럭의 발생을 위한 소정의 제1신호를 출력하는 차동 증폭기 형의 입력 버퍼 수단과; 서로 상이한 전류 구동력을 갖는 두개의 MOS 트랜지스터들을 갖고 상기 입력 버퍼 수단에 전류를 공급하기 위한 전류 공급 수단과; 소정의 제2신호가 셀프 리프레시 모드를 나타내는 것에 응답하여 상기 두개의 MOS 트랜지스터들 중 상대적으로 작은 전류 구동력을 갖는 제1MOS 트랜지스터를 도통시키고, 상기 제2신호가 상기 셀프 리프레시 모드를 나타내지 않는 것에 응답하여 상기 두개의 트랜지스터들 중 상대적으로 큰 전류 구동력을 갖는 제2MOS 트랜지스터를 도통시켜, 상기 전류 공급 수단으로부터 상기 입력 버퍼 수단으로 공급되는 전류량을 조절하는 제어 수단을 포함하는 것을 특징으로 하는 동기형 디램의 클럭 인에이블 버퍼.A differential amplifier type input buffer means for outputting a predetermined first signal for generation of an internal clock in response to input of a predetermined reference voltage signal and an external clock enable signal; Current supply means for supplying current to the input buffer means having two MOS transistors having different current driving forces from each other; In response to a predetermined second signal exhibiting a self refresh mode, conducting a first MOS transistor having a relatively small current driving force among the two MOS transistors, and in response to the second signal not exhibiting the self refresh mode And a control means for conducting a second MOS transistor having a relatively large current driving force among the two transistors to adjust an amount of current supplied from the current supply means to the input buffer means. Enable buffer. 제1항에 있어서, 상기 제어수단은 상기 제2신호가 상기 셀프 리프레시 모드를 나타내지 않을 때 상기 제2MOS 트랜지스터와 함께 상기 제1MOS 트랜지스터를 도통시키는 것을 특징으로 하는 동기형 디램의 클럭 인에이블 버퍼.The clock enable buffer of claim 1, wherein the control means conducts the first MOS transistor together with the second MOS transistor when the second signal does not indicate the self refresh mode. 제1항 또는 제2항에 있어서, 상기 제1 및 제2MOS 트랜지스터들은 PMOS 트랜지스터들로 구성되는 것을 특징으로 하는 동기형 디램의 클럭 인에이블 버퍼.3. The clock enable buffer of claim 1 or 2, wherein the first and second MOS transistors are PMOS transistors. 제1항 또는 제2항에 있어서, 상기 제1 및 제2MOS 트랜지스터들은 NMOS 트랜지스터들로 구성되는 것을 특징으로 하는 동기형 디램의 클럭 인에이블 버퍼.3. The clock enable buffer of claim 1, wherein the first and second MOS transistors are configured of NMOS transistors. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950051493A 1995-12-18 1995-12-18 A clock enable buffer of the synchronous dram KR0154662B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950051493A KR0154662B1 (en) 1995-12-18 1995-12-18 A clock enable buffer of the synchronous dram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950051493A KR0154662B1 (en) 1995-12-18 1995-12-18 A clock enable buffer of the synchronous dram

Publications (2)

Publication Number Publication Date
KR970049242A true KR970049242A (en) 1997-07-29
KR0154662B1 KR0154662B1 (en) 1998-11-16

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100506929B1 (en) * 2002-08-08 2005-08-09 삼성전자주식회사 Input buffer of a synchronous semiconductor memory device
KR100943142B1 (en) * 2003-12-24 2010-02-18 주식회사 하이닉스반도체 Input buffer

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