KR970016614A - Test mode setting circuit of semiconductor device - Google Patents
Test mode setting circuit of semiconductor device Download PDFInfo
- Publication number
- KR970016614A KR970016614A KR1019950031480A KR19950031480A KR970016614A KR 970016614 A KR970016614 A KR 970016614A KR 1019950031480 A KR1019950031480 A KR 1019950031480A KR 19950031480 A KR19950031480 A KR 19950031480A KR 970016614 A KR970016614 A KR 970016614A
- Authority
- KR
- South Korea
- Prior art keywords
- test mode
- signal
- test
- output signal
- inverting
- Prior art date
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- Tests Of Electronic Circuits (AREA)
Abstract
본 발명은 반도체 장치에 관한 것으로, 특히 집적화된 IC를 테스트하기 위한 테스트 모드를 설정하는 회로에 있어서, 테스트 신호를 소정 시간 지연 출력하는 지연수단과, 상기 지연수단의 출력신호를 인버팅시키는 인버팅수단과, 상기 인버팅수단의 출력신호와 상기 테스트 신호를 논리곱 연산하는 논리곱 연산수단 및 입력신호들을 래치하고, 상기 논리곱 연산수단의 출력신호에 응답하여 래치된 값을 출력하는 래치수단을 구비한 것을 특징으로 한다. 본 발명에 의하면, 테스트 모드의 수와 상관없이 하나의 테스트 모드 설정용 외부 핀만이 이용하여 테스트 모드를 설정하도록 함으로써 직접화의 효율을 높일 수 있으며, 공정상의 로드(load)를 줄일 수 있다는 잇점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a circuit for setting a test mode for testing an integrated IC, comprising: delay means for outputting a test signal for a predetermined time delay, and inverting the output signal of the delay means. A latch means for latching an AND signal and an input signal for performing an AND operation on the output signal of the inverting means and the test signal, and outputting a latched value in response to the output signal of the AND product. Characterized in that provided. According to the present invention, it is possible to increase the efficiency of directing and reduce the process load by allowing the test mode to be set using only one test mode setting external pin regardless of the number of test modes. have.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 종래의 반도체 칩의 테스트 모드 설정회로를 설명하기 위한 개략도이다,1 is a schematic diagram for explaining a test mode setting circuit of a conventional semiconductor chip.
제2도는 본 발명에 따른 테스트 모드 설정회로를 설명하기 위한 도면이다.2 is a view for explaining a test mode setting circuit according to the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950031480A KR970016614A (en) | 1995-09-23 | 1995-09-23 | Test mode setting circuit of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950031480A KR970016614A (en) | 1995-09-23 | 1995-09-23 | Test mode setting circuit of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970016614A true KR970016614A (en) | 1997-04-28 |
Family
ID=66615872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950031480A KR970016614A (en) | 1995-09-23 | 1995-09-23 | Test mode setting circuit of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970016614A (en) |
-
1995
- 1995-09-23 KR KR1019950031480A patent/KR970016614A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |