KR970013353A - Capacitor Formation Method of Semiconductor Device - Google Patents

Capacitor Formation Method of Semiconductor Device Download PDF

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Publication number
KR970013353A
KR970013353A KR1019950026723A KR19950026723A KR970013353A KR 970013353 A KR970013353 A KR 970013353A KR 1019950026723 A KR1019950026723 A KR 1019950026723A KR 19950026723 A KR19950026723 A KR 19950026723A KR 970013353 A KR970013353 A KR 970013353A
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South Korea
Prior art keywords
storage node
forming
source
substrate
insulating
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KR1019950026723A
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Korean (ko)
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주문식
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김주용
현대전자산업 주식회사
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Priority to KR1019950026723A priority Critical patent/KR970013353A/en
Publication of KR970013353A publication Critical patent/KR970013353A/en

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  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 소자 제조방법에 관한 것으로 특히 커패시터 용량을 충분히 확보하여 고집적 디램(DRAM) 메모리 소자제조에 적당하도록 한 반도체 소자의 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device in which a capacitor capacity is sufficiently secured to be suitable for manufacturing a highly integrated DRAM (DRAM) memory device.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 커패시터 제조방법은 필드산화막이 형성된 반도체 기판에 게이트 전극을 형성하고 상기 게이트 전극 양측 기판에 소오스/드레인 불순물영역을 형성하는 제1 공정과, 상기 게이트 및 소오스/드레인 불순물영역이 형성된 기판 전면에 제1절연막, 제2절연막, 제3절연막을 차례로 형성하는 제2공정과, 상기 소오스 불순물영역상의 제1, 제2, 제3절연막을 선택적 습식 및 건식 식각으로 제거하여 소오스 불순물영역을 노출시킴과 동시에 상기 노출된 소오스 불순물영역 표면을 요철모양으로 패터닝하는 제3공정과, 상기 전면에 제1스토리지 노드 폴리실리콘을 증착하고 상기 소오스 불순물영역 상측 커패시터 형성영역의 제1스토리지 노드 폴리실리콘상에 제4절연막을 형성하는 제4공정과, 상기 제4절연막이 형성된 기판전면에 제2스토리 노드 폴리실리콘을 선택적으로 제거하여 커패시터의 스토리지 노드를 패터닝하는 제5공정과, 상기 제4, 제3, 제2절연막을 제거함과 동시에 상기 스토리지 노드 표면에 요철을 형성하는 제6공정과, 상기 표면 부위에 요철을 갖는 스토리지 노드가 형성된 기판 전면에 유전체 및 플레이트 전극을 형성하는 제7공정을 포함하여 이루어짐을 특징으로 한다.The capacitor manufacturing method of the semiconductor device of the present invention for achieving the above object is a first step of forming a gate electrode on the semiconductor substrate on which the field oxide film is formed and the source / drain impurity regions on the substrate on both sides of the gate electrode; A second process of sequentially forming a first insulating film, a second insulating film, and a third insulating film on the entire surface of the substrate on which the gate and the source / drain impurity regions are formed; and selectively wetting the first, second, and third insulating films on the source impurity regions. A third process of removing the source impurity region by dry etching and simultaneously patterning the exposed source impurity region surface into an uneven shape, depositing a first storage node polysilicon on the front surface, and forming a capacitor on the source impurity region A fourth step of forming a fourth insulating film on the first storage node polysilicon in the region; and the fourth section. A fifth step of patterning the storage node of the capacitor by selectively removing the second story node polysilicon on the entire surface of the substrate on which the smoke is formed; and removing the fourth, third, and second insulating layers, and unevenness on the surface of the storage node. And a seventh step of forming a dielectric and a plate electrode on the front surface of the substrate on which the storage node having irregularities on the surface portion is formed.

Description

반도체 소자의 커패시터 제조방법Capacitor Manufacturing Method for Semiconductor Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 반도체 소자의 커패시터 제조방법을 나타낸 공정단면도.Figure 2 is a process cross-sectional view showing a capacitor manufacturing method of a semiconductor device of the present invention.

Claims (3)

필드산화막이 형성된 반도체 기판에 게이트 전극을 형성하고 상기 게이트 전극 양측 기판에 소오스/드레인 불순물영역을 형성하는 제1공정과, 상기 게이트 및 소오스/드레인 불순물영역이 형성된 기판 전면에 제1절연막, 제2절연막, 제3절연막을 차례로 형성하는 제2공정과, 상기 소오스 불순물영역상이 제1, 제2, 제3절연막을 선택적 습식 및 건식 식각으로 제거하여 소오스 불순물영역을 노출시킴과 동시에 상기 노출된 소오스 불순물영역 표면을 요철모양으로 패터닝하는 제3공정과, 상기 전면에 제1 스토리지 노드 폴리실리콘을 증착하고 상기 소오스, 불순물영역 상측 커패시터 형성영역의 제1스토리지 노드 폴리실리콘상에 제4 절연막을 형성하는 제4공정과, 상기 제4절연막이 형성된 전면에 제2 스토리지 노드 폴리실리콘을 증착하고 상기 제4절연막의 측면 및 하부에만 남도록 상기 제1, 제2 스토리지 노드 폴리실리콘을 선택적으로 제거하여 커패시터의 스토리지 노드를 패터닝하는 제5공정과, 상기 제4, 제3, 제2절연막을 제거함과 동시에 상기 스토리지 노드 표면에 요철을 형성하는 제6공정과, 상기 표면 부위에 요철을 갖는 스토리지 노드가 형성된 기판 전면에 유전체 및 플레이트 전극을 형성하는 제7공정을 포함하여 이루어짐을 특징으로 하는 반도체 소자의 커패시터 제조방법.Forming a gate electrode on a semiconductor substrate on which a field oxide film is formed and forming source / drain impurity regions on substrates on both sides of the gate electrode; and a first insulating layer and a second insulating layer on an entire surface of the substrate on which the gate and source / drain impurity regions are formed A second process of sequentially forming an insulating film and a third insulating film; and removing the first, second and third insulating films on the source impurity region by selective wet and dry etching to expose the source impurity region and simultaneously expose the source impurity. A third process of patterning the region surface into a concave-convex shape, and a process of depositing a first storage node polysilicon on the front surface and forming a fourth insulating film on the first storage node polysilicon of the source and impurity region upper capacitor formation region. In step 4, a second storage node polysilicon is deposited on the entire surface of the fourth insulating layer, and the fourth insulating layer is deposited. A fifth process of selectively removing the first and second storage node polysilicon so as to remain only at the side and the bottom thereof, and patterning the storage node of the capacitor; and removing the fourth, third, and second insulating layers, and at the same time, the surface of the storage node And a seventh step of forming an unevenness in the substrate, and a seventh step of forming a dielectric and a plate electrode on the front surface of the substrate on which the storage node having the unevenness is formed on the surface portion thereof. 제1항에 있어서, 제1, 제3, 제4절연막은 산화막으로 하고 제2절연막은 질화막으로 형성함을 특징으로 하는 반도체 소자의 커패시터 제조방법.2. The method of claim 1, wherein the first, third, and fourth insulating films are formed of an oxide film and the second insulating film is formed of a nitride film. 제2항에 있어서, 제3공정은 제1, 제2, 제3절연막을 1차로 건식 식각하여 제거한 후, 제2절연막을 일정시간 습식 식각함과 동시에 노출된 소오스 불순물영역 표면을 요철모양을 패터닝함을 특징으로 하는 반도체 소자의 커패시터 제조방법.3. The method of claim 2, wherein the first process removes the first, second, and third insulating layers by primary dry etching, and then wets the second insulating layer for a predetermined time, and simultaneously patternes the uneven surface of the exposed source impurity region. Capacitor manufacturing method of a semiconductor device characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950026723A 1995-08-26 1995-08-26 Capacitor Formation Method of Semiconductor Device KR970013353A (en)

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KR1019950026723A KR970013353A (en) 1995-08-26 1995-08-26 Capacitor Formation Method of Semiconductor Device

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KR1019950026723A KR970013353A (en) 1995-08-26 1995-08-26 Capacitor Formation Method of Semiconductor Device

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KR970013353A true KR970013353A (en) 1997-03-29

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