KR970013116A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR970013116A
KR970013116A KR1019950026845A KR19950026845A KR970013116A KR 970013116 A KR970013116 A KR 970013116A KR 1019950026845 A KR1019950026845 A KR 1019950026845A KR 19950026845 A KR19950026845 A KR 19950026845A KR 970013116 A KR970013116 A KR 970013116A
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KR
South Korea
Prior art keywords
carbon
forming
gate electrode
etching
carbon spacer
Prior art date
Application number
KR1019950026845A
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Korean (ko)
Inventor
이동덕
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950026845A priority Critical patent/KR970013116A/en
Publication of KR970013116A publication Critical patent/KR970013116A/en

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Abstract

본 발명은 LDD 구조를 갖는 반도체 소자 제조 방법에 관한 것으로 게이트 전극 측벽에 경도가 높은 카본 스페이서를 형성하고, 카본 스페이서와 게이트 전극을 마스트로 이용하여 반도체 기판에 고종도확산영역을 형성하는 방법이다. 그로인하여 접합의 누설전류와 디램의 리프레쉬 특성 열화를 방지하고, 공정제어가 용이하다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having an LDD structure, wherein a carbon spacer having high hardness is formed on sidewalls of a gate electrode, and a high-diffusion diffusion region is formed on a semiconductor substrate using the carbon spacer and the gate electrode as a mask. This prevents the leakage current of the junction and the deterioration of the refresh characteristics of the DRAM and facilitates process control.

Description

반도체소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제4도는 본 발명의 실시예에 따라 LDD MOSFET를 제조하는 단계를 도시한 단면도1 through 4 are cross-sectional views illustrating steps of fabricating an LDD MOSFET in accordance with an embodiment of the present invention.

Claims (7)

LDD구조를 갖는 MOSFET 소자에 있어서, 반도체기판의 상부에 게이트산화막과, 게이트전극을 형성하고, 전체구조의 상부에 절연막을 형성하는 단계와, 상기 게이트전극을 마스크로 하여 반도체기판으로 저농도이온을 주입하여 LDD 영역을 형성하는 단계와, 전체 구조 상부에 경도가 좋은 비정질 카본을 증착하고, 이방성 식각하여 게이트 전극 측벽에 카본 스페이서를 형성하는 단계와, 상기 카본 스페이서와 게이트 전극을 바스크로 하여 반도체기판으로 고농도이온을 주입하여 소오스/드레인용 고농도확산영역을 형성하는 단계와, 상기 카본 스페이서를 식각하여 제거하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 형성방법.A MOSFET device having an LDD structure, comprising: forming a gate oxide film and a gate electrode on an upper portion of a semiconductor substrate, forming an insulating layer on an upper portion of the entire structure, and implanting low concentration ions into the semiconductor substrate using the gate electrode as a mask; Forming an LDD region, depositing amorphous carbon having good hardness over the entire structure, and anisotropically etching to form a carbon spacer on the sidewall of the gate electrode, and forming the carbon spacer and the gate electrode as a basal substrate. Forming a high concentration diffusion region for source / drain by implanting high concentration ions; and removing the carbon spacers by etching them. 제1항에 있어서, 상기 비정질 카본을 스퍼터링 방법으로 증착하는 것을 특징으로 하는 반도체소자의 형성방법.The method of claim 1, wherein the amorphous carbon is deposited by a sputtering method. 제1항에 있어서, 상기 비정질 카본을 이방성 식각할 때 10m Torr 이하의 저압과 O2/Ar 혹은 O2/CO 가스계를 사용하는 것을 특징으로 하는 반도체소자의 형성방법.The method of claim 1, wherein the anisotropic etching of the amorphous carbon uses a low pressure of 10 m Torr or less and an O 2 / Ar or O 2 / CO gas system. 제1항에 있어서, 상기 카본 스페이서를 습식식각으로 제거하는 것을 특징으로 하는 반도체소자의 형성방법.The method of claim 1, wherein the carbon spacer is removed by wet etching. 제1항에 있어서, 상기 카본 스페이서를 제거하는 단계에서 플라즈마 식각장비로 10m Torr 이상의 압력과 O2를 포함하는 가스계를 사용한 것을 특징으로 하는 반도체소자의 형성방법.The method of claim 1, wherein the removing of the carbon spacer comprises using a gas system including a pressure of 10 m Torr or more and O 2 as a plasma etching equipment. 제1항에 있어서, 상기 절연막은 최대 200Å 두께로 증착하는 것을 특징으로 하는 반도체소자의 형성방법.The method of claim 1, wherein the insulating layer is deposited to a maximum thickness of 200 μm. 제1항에 있어서, 상기 카본 스페이서는 절연막에 대하여 식각선택비가 50 : 1 정도인 것을 특징으로 하는 반도체소자의 형성방법.The method of claim 1, wherein the carbon spacer has an etching selectivity of about 50: 1 with respect to the insulating film.
KR1019950026845A 1995-08-28 1995-08-28 Manufacturing method of semiconductor device KR970013116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950026845A KR970013116A (en) 1995-08-28 1995-08-28 Manufacturing method of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950026845A KR970013116A (en) 1995-08-28 1995-08-28 Manufacturing method of semiconductor device

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271594B1 (en) 1997-05-29 2001-08-07 Nec Corporation Semiconductor device and method of manufacturing the same
KR100743629B1 (en) * 2005-09-29 2007-07-27 주식회사 하이닉스반도체 Method of manufacturing semiconductor device
KR20180091939A (en) * 2016-01-05 2018-08-16 어플라이드 머티어리얼스, 인코포레이티드 Method for fabricating nanowires for horizontal gate allround devices for semiconductor applications

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271594B1 (en) 1997-05-29 2001-08-07 Nec Corporation Semiconductor device and method of manufacturing the same
KR100298915B1 (en) * 1997-05-29 2001-10-19 가네꼬 히사시 Semiconductor device and method of manufacturing the same
KR100743629B1 (en) * 2005-09-29 2007-07-27 주식회사 하이닉스반도체 Method of manufacturing semiconductor device
KR20180091939A (en) * 2016-01-05 2018-08-16 어플라이드 머티어리얼스, 인코포레이티드 Method for fabricating nanowires for horizontal gate allround devices for semiconductor applications

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