KR970013052A - Via contact formation method of semiconductor device - Google Patents

Via contact formation method of semiconductor device Download PDF

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Publication number
KR970013052A
KR970013052A KR1019950027387A KR19950027387A KR970013052A KR 970013052 A KR970013052 A KR 970013052A KR 1019950027387 A KR1019950027387 A KR 1019950027387A KR 19950027387 A KR19950027387 A KR 19950027387A KR 970013052 A KR970013052 A KR 970013052A
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KR
South Korea
Prior art keywords
metal layer
lower metal
forming
semiconductor device
via contact
Prior art date
Application number
KR1019950027387A
Other languages
Korean (ko)
Other versions
KR0170910B1 (en
Inventor
김상영
Original Assignee
김주용
현대전자산업주식회사
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Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019950027387A priority Critical patent/KR0170910B1/en
Publication of KR970013052A publication Critical patent/KR970013052A/en
Application granted granted Critical
Publication of KR0170910B1 publication Critical patent/KR0170910B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 비아콘택 형성방법에 관한 것으로, 반도체기판 상부에 층간절연막을 형성하고 그 상부에 하부금속층 및 반사방지막을 순차적으로 형성한 다음, 마스크를 이용한 식각공정으로 콘택플러그 형성의 하부금속층을 형성하고 전체표면상부에 금속층간절연막을 형성한 다음, CMP 공정으로 상기 하부금속층을 노출시키고 상기 하부금속층에 접속되는 상부금속층을 형성하여 안정된 비아콘택을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술이다.The present invention relates to a method for forming a via contact of a semiconductor device. The interlayer insulating film is formed on a semiconductor substrate, and a lower metal layer and an anti-reflection film are sequentially formed on the semiconductor substrate, and a lower metal layer of a contact plug is formed by an etching process using a mask. And the interlayer dielectric layer on the entire surface, and then expose the lower metal layer by CMP process and form the upper metal layer connected to the lower metal layer to form stable via contact to improve the characteristics and reliability of the semiconductor device. It is a technology that can.

Description

반도체 소자의 비아콘택 형성방법Via contact formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 실시예에 따른 반도체 소자의 비아콘택 형성방법을 도시한 단면도.2A through 2D are cross-sectional views illustrating a method for forming a via contact of a semiconductor device in accordance with an embodiment of the present invention.

Claims (2)

단위 셀이 구비된 반도체기판 상부에 금속배선을 형성하기 위한 층간절연막을 증착하는 공정과, 상기 층간절연막 상부에 하부금속층을 형성하는 공정과, 상기 하부금속층 상부에 반사방지막을 형성하는 공정과, 마스크를 이용한 식각공정으로 상기 반사방지막과 하부금속층을 순차적으로 식각하여 콘택플러그 형상의 하부금속층을 형성하는 공정과, 전체표면상부에 금속층간절연막을 형성하는 공정과, CMP 공정으로 상기 콘택플러그 형상 상부의 금속층간절연막을 제거하는 공정과, 상기 하부금속층에 접속되는 상부금속층을 형성하는 공정을 포함하는 반도체 소자의 비아콘택 형성방법.Depositing an interlayer insulating film for forming metal wiring on the semiconductor substrate provided with unit cells, forming a lower metal layer on the interlayer insulating film, forming an anti-reflection film on the lower metal layer, and a mask Etching the anti-reflective film and the lower metal layer sequentially to form a contact plug-shaped lower metal layer by etching, forming an intermetallic insulating layer on the entire surface, and CMP process A method of forming a via contact in a semiconductor device, the method comprising removing a metal interlayer insulating film and forming an upper metal layer connected to the lower metal layer. 제1항에 있어서, 상기 금속층간절연막은 TEOS 산화막으로 형성되는 것을 특징으로 하는 반도체 소자의 비아콘택 형성방법.The method of claim 1, wherein the interlayer dielectric film is formed of a TEOS oxide film.
KR1019950027387A 1995-08-30 1995-08-30 Bia contact forming method of semiconductor device KR0170910B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950027387A KR0170910B1 (en) 1995-08-30 1995-08-30 Bia contact forming method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950027387A KR0170910B1 (en) 1995-08-30 1995-08-30 Bia contact forming method of semiconductor device

Publications (2)

Publication Number Publication Date
KR970013052A true KR970013052A (en) 1997-03-29
KR0170910B1 KR0170910B1 (en) 1999-03-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950027387A KR0170910B1 (en) 1995-08-30 1995-08-30 Bia contact forming method of semiconductor device

Country Status (1)

Country Link
KR (1) KR0170910B1 (en)

Also Published As

Publication number Publication date
KR0170910B1 (en) 1999-03-30

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