KR20010003760A - Method of forming wiring for semiconductor device - Google Patents

Method of forming wiring for semiconductor device Download PDF

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Publication number
KR20010003760A
KR20010003760A KR1019990024191A KR19990024191A KR20010003760A KR 20010003760 A KR20010003760 A KR 20010003760A KR 1019990024191 A KR1019990024191 A KR 1019990024191A KR 19990024191 A KR19990024191 A KR 19990024191A KR 20010003760 A KR20010003760 A KR 20010003760A
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South Korea
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film
insulating film
forming
wiring
semiconductor device
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KR1019990024191A
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Korean (ko)
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KR100299521B1 (en
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이태국
조찬섭
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김영환
현대전자산업 주식회사
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps

Abstract

PURPOSE: A method for forming a wire of a semiconductor device is provided to prevent the signal delay by reducing the capacitance between wires. CONSTITUTION: The first insulation film(22) is formed on a semiconductor substrate(20) formed with a lower wiring layer(21). A sacrificial layer for exposing the first insulation film(22) is formed on the first insulation film(22). Then, the second insulation film(24A) is coated on the first insulation film(22). A contact hole is formed by etching the second and first insulation films(24A,22). Then, a metal film is formed on the second insulation film(24A). After that, an upper wiring layer(26A) making contact with the lower wiring layer(21) is formed by a blanket etching process. The third insulation film(27A) is formed on the second insulation film(24A). Then, the third and second insulation films(27A,24A) are etched such that the sacrificial film pattern is exposed thereby forming a damascne structure. Then, the first insulation film(22) is exposed by removing the sacrificial film pattern. After that, the fourth insulation film(28) is formed so as to form an air gap between the damascne structure.

Description

반도체 소자의 배선 형성방법{Method of forming wiring for semiconductor device} Wiring formation method of a semiconductor device {Method of forming wiring for semiconductor device}

본 발명은 반도체 소자의 배선 형성방법에 관한 것으로, 특히 데머신 구조 및 에어갭을 동시에 적용한 새로운 반도체 소자의 배선 형성방법에 관한 것이다. The present invention relates to a wiring forming method of the new semiconductor device by applying, in particular for machine structure and the air gap on the wiring formation method of a semiconductor device at the same time.

반도체 소자의 고집적화에 따라 배선 사이의 간격이 미세해지고 있다. There is a gap between the wiring becomes fine, depending on the degree of integration of semiconductor devices. 한편, 이러한 배선들 사이의 절연을 위하여 사용되는 절연물질의 높은 유전상수(K)로 인하여 배선 사이의 캐패시턴스가 증가되어 신호지연(RC-Delay) 현상이 발생됨으로써 소자의 특성이 저하된다. On the other hand, those due to the high dielectric constant (K) of the insulating material used for the insulation between the wirings is increased the capacitance between the signal wiring delay (RC-Delay) phenomenon occurs, whereby the characteristic of the device is lowered.

따라서, 배선 사이의 캐패시턴스를 낮추기 위하여, 유전상수가 낮은 에어갭(air gap)을 이용하여 배선사이를 절연시키는 기술(Solid State Technology 1999 February Page 51 " Air Gap Lower k of interconnect dielectrics")이 제시되었다. Therefore, to keep the capacitance between the wiring, the dielectric constant has been proposed the technology (Solid State Technology 1999 February Page 51 "Air Gap Lower k of interconnect dielectrics") for insulation between the wirings by using a lower air gap (air gap) .

도 1a 내지 도 1d는 일본의 마쯔시다에서 제시한 종래의 에어-갭을 이용한 반도체 소자의 배선 형성방법을 설명하기 위한 단면도이다. Figure 1a to 1d is a conventional air presented in the Japanese Matsushita - a sectional view illustrating a wiring forming method for a semiconductor device using the gap.

도 1a를 참조하면, 상부에 제 1 산화막(11)이 형성된 반도체 기판(10) 상에제 1 도전막(12)을 증착하고, 제 1 도전막(12) 상부에 제 2 산화막(13)을 형성한다. Referring to Figure 1a, a first oxide film 11 is formed, the semiconductor substrate 10, the first conductive film 12, the second oxide film 13, the upper part of the deposition, the first conductive film 12 a on the upper forms. 그런 다음, 제 1 도전막(12)의 일부가 노출되도록 제 2 산화막(13)을 식각하여 콘택홀을 형성하고, 상기 콘택홀에 매립됨과 동시에 제 2 산화막(13)의 표면으로부터 돌출된 플러그(14)를 형성한다. Then etching Next, the second oxide film 13 to partially expose the conductive film 12 as soon form the contact holes, and embedded in the contact hole a plug projecting at the same time from the surface of the second oxide film 13 ( 14) to form. 그런 다음, 제 2 산화막(13) 상에 제 2 산화막(13)의 일부를 노출시키는 레지스트 패턴(15A, 15B, 15C, 15D)을 형성한다. In that form and then the second oxide film 13, a resist pattern (15A, 15B, 15C, 15D) that exposes a portion of the second oxide film 13 on. 여기서, 레지스트 패턴(15) 중 하나(15B)는 플러그(14)의 일부분을 덮도록 한다. One where the resist pattern (15) (15B) is so as to cover a portion of the plug 14.

도 1b를 참조하면, 레지스트 패턴(15A, 15B, 15C, 15D) 및 플러그(14)를 마스크로하여 제 2 산화막(13) 및 제 1 도전막(12)을 과도식각으로 식각하여, 하부 배선층(12A, 12B, 12C, 12D)을 형성함과 동시에 제 1 산화막(11)을 일부 두께만큼 식각한다. Referring to Figure 1b, to a resist pattern (15A, 15B, 15C, 15D) and the plug (14) as a mask by etching the second oxide film 13 and the first conductive film 12 by excessive etching, the lower wiring layer ( 12A, box 12B, 12C, 12D) for forming and at the same time, etching the first oxide film 11 as a part thickness. 그런 다음, 공지된 방법으로 레지스트 패턴(15A, 15B, 15C, 15D)을 제거하고, 도 1c에 도시된 바와 같이, 도 1b의 구조 상에 플라즈마 보조 화학기상증착(Plasma Enahnced Chemical Vapor Deposition; PECVD)으로 제 3 산화막(16)을 증착한다. Then, the resist pattern (15A, 15B, 15C, 15D) by a known method, and a plasma assisted chemical vapor deposited over the structure of Figure 1b, as shown in Fig. 1c (Plasma Enahnced Chemical Vapor Deposition; PECVD) as to deposit a third oxide layer (16). 이때, 제 3 산화막(16)은 미세 간격을 갖는 하부 배선층(12A, 12B, 12C, 12D) 사이에는 매립되지 않으므로, 에어갭(AG)이 발생된다. In this case, the third oxide layer 16 is not embedded between the fine interval the lower wiring layer (12A, 12B, 12C, 12D) having, an air gap (AG) is generated. 그리고 나서, 기판 전면에 표면을 평탄화시키기 위하여 고밀도 플라즈마 화학기상증착(High Density Plasma CVD; HDP-CVD)로 제 4 산화막(17)을 증착한다. Then, the high-density plasma CVD (High Density Plasma CVD; HDP-CVD) so as to planarize a surface over the entire surface of the substrate and depositing a fourth oxide layer 17 to the.

도 1d를 참조하면, 제 4 산화막(17)을 플러그(14)가 노출되도록 전면식각하고, 전면식각된 제 4 산화막(17A) 상부에 제 2 도전막을 증착하고 패터닝하여 상부 배선(18)을 형성한다. Referring to Figure 1d, the fourth form an oxide film 17, a plug 14 and a second conductive upper wire (18) by depositing and patterning films on the upper front face etching, and the front-etching the fourth oxide layer (17A) so as to expose do.

즉, 제 3 산화막(16)에 의해 발생된 에어갭(AG)에 의해 미세 간격을 갖는 배선들(12A, 12B, 12C, 12D)이 전기적으로 절연될 뿐만 아니라 에어의 낮은 유전율에 의해 배선 사이의 캐패시턴스가 감소됨으로써, 신호지연 현상이 방지된다. That is, between the third wires having a small interval by an air gap (AG) caused by the oxide film (16) (12A, 12B, 12C, 12D) are wires by an electrical low dielectric constant of the air as well as to be insulated from By the capacitance decreasing, the signal delay is prevented.

한편, 상기한 바와 같이 양각공정에 의해 형성된 배선은, 도전막의 식각특성이 열악한 경우 인접 배선과의 브리지가 발생되고, 이러한 브리지는 소자의 고집적화에 따라 더욱더 심각해진다. On the other hand, when the wiring is formed by the embossing process as described above, the conductive film is poor etching characteristics, and the bridge between the adjacent wiring occurs, this bridge becomes more and more serious depending on the degree of integration of the device. 이에 대하여, 최근에는 데머신(damascne) 구조를 이용하여 배선을 형성하는 방법이 제시되었으나, 이러한 데머신 구조에서는 배선이 절연막 내에 완전히 매립되어 형성되기 때문에 배선 사이의 브리지는 방지되지만, 에어갭을 적용하기가 어렵기 때문에, 배선 사이의 캐패시턴스가 높다. On the other hand, in recent years, to the machine (damascne), but presents a method of forming wiring using the structure, the bridge between the wiring, but the prevention because this to the machine structure, the wiring is formed completely buried in the insulating layer, applying an air gap since it is difficult for high capacitance between the wirings.

따라서, 본 발명은 에어갭 및 데머신 구조로 동시에 적용하여 배선 사이의 캐패시턴스를 감소시키고 배선 사이의 브리지를 방지할 수 있는 고집적화에 용이한 반도체 소자의 배선 형성방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide an easy method of forming wiring of a semiconductor device in which integration is possible to reduce the capacitance between the wiring applied to the air gap and to the machine structure at the same time and to prevent the bridge between the wiring.

도 1a 및 도 1d는 종래의 에어-갭을 갖는 반도체 소자의 배선 형성방법을 설명하기 위한 단면도. Figure 1a and Figure 1d is a conventional air-sectional view illustrating a wiring forming method for a semiconductor device having a gap.

도 2a 내지 도 2j는 본 발명의 실시예에 따른 따른 데머신 구조 및 에어-갭을 갖는 반도체 소자의 배선 형성방법을 설명하기 위한 단면도. Figures 2a-2j is for machine structure and the air according to according to an embodiment of the present invention cross-sectional view illustrating a wiring forming method for a semiconductor device having a gap.

(도면의 주요 부분에 대한 부호의 설명) (Description of the Related Art)

20 : 반도체 기판 21 : 하부 배선층 20: Semiconductor substrate 21: a lower wiring layer

22 : 제 1 절연막 23A : 희생막 패턴 22: first insulating layer 23A: sacrificial layer pattern

24, 24A : 제 2 절연막 25 : 콘택홀 24, 24A: a second insulating film 25: contact hole

26 : 도전막 26A : 상부 배선층 26: conductive layer 26A: upper wiring layer

27, 27A : 제 3 절연막 28 : 제 4 절연막 27, 27A: a third insulating film 28: fourth insulating film

100 : 데머신 구조 AG : 에어갭 100: for machine structure AG: the air gap

상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따라 하부 배선층이 구비된 반도체 기판 상에 제 1 절연막을 형성하고, 제 1 절연막 상에 하부 배선층 상의 제 1 절연막을 노출시키는 희생막 패턴을 형성한다. According to an aspect of the present invention, forming a pattern the sacrificial layer to form a first insulating film on the semiconductor substrate having the lower wiring layer and the exposed first insulating layer on the lower wiring on the first insulating film according to the present invention do. 그런 다음, 희생막 패턴 및 노출된 제 1 절연막 표면에 제 2 절연막을 형성하고, 하부 배선층의 일부가 노출되도록 제 2 및 제 1 절연막을 식각하여 콘택홀을 형성한 후, 콘택홀에 매립되도록 제 2 절연막 상에 배선용 금속막을 형성한다. Then, after forming a second insulating film on the surface of the first insulating film a sacrificial layer pattern, and exposure, and a portion of the lower wiring layer is exposed by etching the second and first insulating film to form a contact hole, so that embedded in the contact hole, the to form a wiring metal film on the second insulating film. 그리고 나서, 금속막을 제 2 절연막의 표면 및 제 2 절연막 상의 콘택홀의 일부가 노출되도록 블랭킷 식각하여, 콘택홀을 통하여 하부 배선층과 콘택하는 상부 배선층을 형성하고, 노출된 콘택홀에 매립되도록 제 2 절연막 상부에 제 3 절연막을 형성한다. Then, the second insulating film so that the metal to prevent the blanket etched to expose the surface and some contact holes on the second insulating film of the second insulating film, forming an upper wiring layer to lower wiring layer and the contact through the contact holes, and embedded in the exposed contact holes to form a third insulating film on the top. 그런 다음, 제 3 및 제 2 절연막을 희생막 패턴이 노출되도록 전면식각하여 제 1 내지 제 3 절연막에 의해 상부 배선층이 둘러싸인 데머신 구조를 형성하고, 희생막 패턴을 제거하여 제 1 절연막을 노출시킨다. And then, the third and the forming machine structure having surrounded the upper wiring layer by the first to third insulating film by the front etching so that the film pattern is exposed to the expense of the second insulating film, and removing the pattern the sacrificial layer to expose the first insulating layer . 그 후, 데머신 구조 사이에는 매립되지 않도록 기판 전면에 제 4 절연막을 형성하여 상기 데머신 구조 사이에 에어갭을 형성한다. Then, to the machine structure is formed between the air gap between to form a fourth insulating film on the substrate surface from being filled to the machine structure.

본 실시예에서, 희생막 패턴은 제 1 내지 제 3 절연막에 대한 식각 선택비가 높은 막으로서, PSG막, BPSG막, USG막, SiON막과 같은 산화막 또는 도핑되지 않은 폴리실리콘막으로 형성한다. In this embodiment, a sacrificial layer pattern is first to the ratio of high film etching selectivity for the third insulating film to form a PSG film, a BPSG film, a USG film, oxide film or a non-doped polysilicon film such as a SiON film. 또한, 제 4 절연막은 플라즈마 보조 화학기상증착에 의한 산화막으로 형성한다. Further, a fourth insulating film to form an oxide film by plasma assisted chemical vapor deposition.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다. With reference to the accompanying drawings, a description will be given of an embodiment of the present invention.

도 2a 내지 도 2j는 본 발명의 실시예에 따른 반도체 소자의 배선 형성방법을 설명하기 위한 단면도. Figures 2a-2j is a sectional view for explaining a wiring method for forming a semiconductor device according to an embodiment of the present invention.

도 2a를 참조하면, 하부 배선층(21)이 구비한 반도체 기판(20) 상에 제 1 절연막(22)을 형성하고, 제 1 절연막(22) 상부에 절연막에 대한 식각선택비가 우수한 희생막(23)을 형성한다. Referring to Figure 2a, the lower wiring layer 21 is a semiconductor substrate 20 on the first insulating film 22 in the formation, and the first insulating film 22 is an excellent choice etching of the upper insulating film ratio of the sacrificial film (23 a having ) to form. 바람직하게, 희생막(23)은 PSG막, BPSG막, USG막, SiON막과 같은 산화막 또는 도핑되지 않은 폴리실리콘막으로 형성한다. Preferably, the sacrifice film 23 is formed of a PSG film, a BPSG film, a USG film, oxide film or a non-doped polysilicon film such as a SiON film. 도 2b를 참조하면, 하부 배선층(21) 상의 제 1 절연막(22)이 노출되도록 희생막(23)을 식각하여 희생막 패턴(23A)을 형성한다. Referring to Figure 2b, the first insulating film 22 on the lower wiring layer 21 is etched to the sacrificial layer 23 is exposed to form a sacrificial film pattern (23A). 그런 다음, 도 2c에 도시된 바와 같이, 희생막 패턴(23A) 및 노출된 제 1 절연막(22)의 표면에 제 2 절연막(24)을 형성하고, 하부 배선층(21)의 일부가 노출되도록 제 2 절연막(24) 및 제 1 절연막(22)을 식각하여 콘택홀(25)을 형성한다. As then shown in Figure 2c, part of the sacrificial film pattern (23A) and forming a second insulating film 24 on the surface of the exposed first insulation film 22, and the lower wiring layer 21 is to be exposed to the etching the second insulating film 24 and the first insulating film 22 to form a contact hole 25.

도 2e를 참조하면, 콘택홀(25)에 매립되도록 제 2 절연막(24) 상에 배선용 금속막(26)을 형성한다. Referring to Figure 2e, to form a contact hole 25, a wiring metal film 26 on the second insulating film 24 to be buried in. 그런 다음, 도 2f에 도시된 바와 같이, 제 2 절연막(24)의 표면 및 제 2 절연막(25) 상의 콘택홀(25)의 일부가 노출되도록 금속막(26)을 블랭킷 식각하여, 콘택홀(25)을 통하여 하부 배선층(21)과 콘택하는 상부 배선층(26A)을 형성한다. Then, as shown in Fig. 2f, the second insulating film 24 surface and a blanket etch the contact hole metal film 26 so that part of the impression (25) on the second insulating film 25 in the contact hole ( 25) to form a lower wiring layer 21 and contact the upper wiring layer (26A) which through.

도 2g를 참조하면, 노출된 콘택홀(25)에 매립되도록 제 2 절연막(24) 상부에 제 3 절연막(27)을 형성하고, 도 2h에 도시된 바와 같이, 희생막 패턴(23A)이 노출되도록 제 3 절연막(27) 및 제 2 절연막(24)을 화학기계연마(Chemical Mechanical Polishing; CMP)로 전면 식각하여, 제 1 내지 제 3 절연막(22, 24A. 27A)에 의해 상부 배선층(26A)이 둘러싸인 데머신 구조(100)를 형성함과 동시에, 제 1 절연막(22) 상에서 제 2 절연막(24A) 및 제 3 절연막(27A)을 이격시킨다. Referring to Figure 2g, and forming a third insulating film 27 on the upper second insulating film 24 to be embedded in the exposed contact hole 25, as shown in Figure 2h, the sacrificial film pattern (23A) is exposed such that the third insulating film 27 and second insulating film 24 to chemical mechanical polishing (chemical Mechanical polishing; CMP) in the front of the etching, the first to third insulating film above the wiring layer (26A) by the (. 22, 24A 27A) and at the same time it is enclosed to form the machine structure 100, the thereby space the second insulating film (24A) and a third insulating film (27A) on the first insulating film 22.

도 2i에 도시된 바와 같이, 희생막 패턴(23A)을 제거하여, 제 1 절연막(22)을 노출시킨다. Be as shown in 2i, removing the sacrificial film pattern (23A), thereby exposing the first insulation film (22). 예컨대, 희생막 패턴(23A)이 PSG막, BPSG막, USG막, SiON막과 같은 산화막으로 이루어진 경우에는 습식식각으로 제거하고, 도핑되지 않은 폴리실리콘막으로 이루어진 경우에는 건식식각으로 제거한다. For example, in the case made of a case made of an oxide film such as a PSG film sacrificial layer pattern (23A), BPSG film, USG film, SiON film is removed by wet etching, and an undoped polysilicon film is removed by dry etching. 그리고 나서, 도 2j에 도시된 바와 같이, 도 2i의 구조 상에 제 4 절연막(28)을 형성한다. Then, to form a fourth insulating film 28 on the structure of Figure 2i as shown in Figure 2j. 바람직하게, 제 4 절연막(28)은 PECVD에 의한 산화막으로 형성한다. Preferably, the fourth insulating film 28 is formed of an oxide film by PECVD. 이때, 제 4 절연막(28)은 데머신 구조(100) 사이에는 매립되지 않으므로, 데머신 구조(100) 사이에 에어갭(AG)이 형성된다. At this time, the fourth insulating film 28 is used is not embedded between the machine structure 100, the air gap (AG) is formed between the machine to the structure 100.

상기한 본 발명에 의하면, 절연막에 대한 식각선택비가 우수한 희생막을 이용하여 절연막에 의해 배선이 둘러싸인 데머신 구조를 형성하고, 데머신 구조 사이에 에어갭을 형성함으로써, 배선 사이의 브리지가 방지됨과 동시에 에어의 낮은 유전율에 의해 배선 사이의 캐패시턴스가 감소되어 신호지연 현상이 방지된다. According to the present invention described above, by using a film etch selectivity ratio is high expense for the insulation film to form the machine structure having wiring is surrounded by an insulating film, having formed an air gap between the machine structure, as soon prevent a bridge between the wiring at the same time by the low dielectric constant of air is the capacitance between the wiring is reduced signal delay can be prevented. 결과로서, 소자의 특성이 향상된다. As a result, an improvement in characteristics of the element.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다. In addition, the present invention can be carried out by various modifications without departing from the present invention is not limited to the above-described embodiment, the technical spirit of the present invention.

Claims (8)

  1. 하부 배선층이 구비된 반도체 기판 상에 제 1 절연막을 형성하는 단계; Further comprising: a lower wiring layer to form a first insulating film on a semiconductor substrate comprising;
    상기 제 1 절연막 상에 상기 하부 배선층 상의 제 1 절연막을 노출시키는 희생막 패턴을 형성하는 단계; Forming a sacrificial layer pattern to expose the first insulating layer on the lower wiring on the first insulating film;
    상기 희생막 패턴 및 노출된 제 1 절연막 표면에 제 2 절연막을 형성하는 단계; Forming a second insulating film on the surface of the first insulating film, the sacrificial film pattern and exposure;
    상기 하부 배선층의 일부가 노출되도록 상기 제 2 및 제 1 절연막을 식각하여 콘택홀을 형성하는 단계; Step by etching the second and first insulating film to form a contact hole, a part of the lower wiring layer is exposed;
    상기 콘택홀에 매립되도록 상기 제 2 절연막 상에 배선용 금속막을 형성하는단계; Forming a wiring metal film on the second insulating layer such that the buried in the contact holes;
    상기 금속막을 상기 제 2 절연막의 표면 및 상기 제 2 절연막 상의 콘택홀의 일부가 노출되도록 블랭킷 식각하여, 상기 콘택홀을 통하여 상기 하부 배선층과 콘택하는 상부 배선층을 형성하는 단계; Forming an upper wiring layer to contact said lower wiring layer and the metal film is etched such that the blanket and the surface portion is exposed to the contact hole on the second insulation film of the second insulating film, through the contact holes;
    상기 노출된 콘택홀에 매립되도록 상기 제 2 절연막 상부에 제 3 절연막을 형성하는 단계; Forming a third insulating film above the second insulating film to be buried in the exposed contact holes;
    상기 제 3 및 제 2 절연막을 상기 희생막 패턴이 노출되도록 전면식각하여 상기 제 1 내지 제 3 절연막에 의해 상기 상부 배선층이 둘러싸인 데머신 구조를 형성하는 단계; The third and the second step of etching the front so that the sacrificial layer pattern to expose the second insulating film forming the first to the machine structure to the upper wiring layer is surrounded by the third insulating film;
    상기 희생막 패턴을 제거하여 상기 제 1 절연막을 노출시키는 단계; Exposing the first insulating film by removing the sacrificial film pattern; And
    상기 데머신 구조 사이에는 매립되지 않도록 상기 기판 전면에 제 4 절연막을 형성하여 상기 데머신 구조 사이에 에어갭을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 배선 형성방법. Wiring formation method of a semiconductor device comprising the steps of forming from being buried between the machine having the structure to form a fourth insulating film on the substrate surface to the air gap between the machine structure.
  2. 제 1 항에 있어서, 상기 희생막 패턴은 상기 제 1 내지 제 3 절연막에 대한 식각 선택비가 높은 막으로 형성하는 것을 특징으로 하는 반도체 소자의 배선 형성방법. The method of claim 1, wherein the sacrificial layer pattern wiring forming method of the semiconductor device so as to form with the first high etch selection ratio to the film of the third insulating film.
  3. 제 1 항 또는 제 2 항에 있어서, 상기 희생막 패턴은 PSG막, BPSG막, USG막, SiON막과 같은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 배선 형성방법. According to claim 1 or 2, wherein the wiring formation method of a semiconductor device characterized in that formed in the sacrificial layer pattern PSG film, BPSG film, a USG film, an oxide film such as a SiON film.
  4. 제 3 항에 있어서, 상기 희생막 패턴은 습식식각으로 제거하는 것을 특징으로 하는 반도체 소자의 배선 형성방법. The method of claim 3, wherein the wiring formation method of a semiconductor device which is characterized in that the sacrificial layer pattern is removed by wet etching.
  5. 제 1 항 또는 제 2 항에 있어서, 상기 희생막 패턴은 도핑되지 않은 폴리실리콘막으로 형성하는 것을 특징으로 하는 반도체 소자의 배선 형성방법. According to claim 1 or 2, wherein the wiring formation method of a semiconductor device characterized in that formed in the sacrificial layer pattern is non-doped polysilicon film.
  6. 제 5 항에 있어서, 상기 희생막 패턴은 건식식각으로 제거하는 것을 특징으로 하는 반도체 소자의 배선 형성방법. The method of claim 5, wherein the wiring formation method of a semiconductor device characterized in that the removal of the sacrificial film pattern is dry etched.
  7. 제 1 항에 있어서, 상기 제 2 및 제 3 절연막의 전면식각은 화학기계연마로 진행하는 것을 특징으로 하는 반도체 소자의 배선 형성방법. The method of claim 1, wherein forming the wiring of a semiconductor device characterized in that the process proceeds to the second front and etching is chemical mechanical polishing of the third insulating film.
  8. 제 1 항에 있어서, 상기 제 4 절연막은 플라즈마 보조 화학기상증착에 의한 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 배선 형성방법. The method of claim 1, wherein the wiring formation method of a semiconductor device which comprises forming a fourth insulating film is an oxide film by plasma assisted chemical vapor deposition.
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KR100680421B1 (en) * 2004-01-05 2007-02-08 주식회사 하이닉스반도체 Method for Manufacturing Metal line for Semi Conductor Using Tunneling
WO2008036385A1 (en) * 2006-09-21 2008-03-27 Intel Corporation Dielectric spacers for metal interconnects and method to form the same
US7649239B2 (en) 2006-05-04 2010-01-19 Intel Corporation Dielectric spacers for metal interconnects and method to form the same
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US9960110B2 (en) 2011-12-30 2018-05-01 Intel Corporation Self-enclosed asymmetric interconnect structures

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Publication number Priority date Publication date Assignee Title
KR100680421B1 (en) * 2004-01-05 2007-02-08 주식회사 하이닉스반도체 Method for Manufacturing Metal line for Semi Conductor Using Tunneling
US7649239B2 (en) 2006-05-04 2010-01-19 Intel Corporation Dielectric spacers for metal interconnects and method to form the same
US7923760B2 (en) 2006-05-04 2011-04-12 Intel Corporation Dielectric spacers for metal interconnects and method to form the same
US8394701B2 (en) 2006-05-04 2013-03-12 Intel Corporation Dielectric spacers for metal interconnects and method to form the same
WO2008036385A1 (en) * 2006-09-21 2008-03-27 Intel Corporation Dielectric spacers for metal interconnects and method to form the same
US7772702B2 (en) 2006-09-21 2010-08-10 Intel Corporation Dielectric spacers for metal interconnects and method to form the same
US9960110B2 (en) 2011-12-30 2018-05-01 Intel Corporation Self-enclosed asymmetric interconnect structures
US8772938B2 (en) 2012-12-04 2014-07-08 Intel Corporation Semiconductor interconnect structures
US9064872B2 (en) 2012-12-04 2015-06-23 Intel Corporation Semiconductor interconnect structures
US9455224B2 (en) 2012-12-04 2016-09-27 Intel Corporation Semiconductor interconnect structures
US9754886B2 (en) 2012-12-04 2017-09-05 Intel Corporation Semiconductor interconnect structures

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