KR970008927A

KR970008927A - Carrier Frequency Error Correction Circuit of Satellite Broadcasting System

Info

Publication number: KR970008927A
Application number: KR1019950020846A
Authority: KR
Inventors: 유용태
Original assignee: 구자홍; Lg 전자 주식회사
Priority date: 1995-07-14
Filing date: 1995-07-14
Publication date: 1997-02-24
Also published as: KR0161916B1

Abstract

본 발명은 위성방송 수신시스템에 관한 것으로, 특히 QPSK(Quadrature Phase Shift Keying)복조부의 캐리어 주파수 에러(Carrier Frequency Error)를 효율적으로 보상할 수 있는 위성방송 수신시스템의 캐리어(Carrier)주파수오차 보정회로에 관한 것이다.The present invention relates to a satellite broadcasting receiving system, and more particularly, to a carrier frequency error correction circuit of a satellite broadcasting receiving system capable of efficiently compensating a carrier frequency error of a quadrature phase shift keying (QPSK) demodulator. It is about.

상기와 같은 본 발명의 위성방송 수신시스템의 캐리어(Carrier)주파수오차 보정회로는 시스템 전체를 제어하는 마이컴과, 상기 마이컴의 제어에 의해 오차가 보정된 발진주파수를 출력하는 PLL 회로부와, 안테나를 통하여 위성으로부터 송신된 신호를 수신하여 일정레벨 이상으로 증폭하는 저잡음 증폭기와, 믹싱되어 출력되는 저잡음 증폭기와 PLL회로부의 출력신호를 필터링하여 다른 대역의 노이즈를 제거하는 BPF와, 상기 대역통과 필터링된 1채널신호와 π/2위상천이된 내부의 발진주파수를 믹싱하는 제1믹서, Q 채널신호와 내부 발진 주파수를 믹싱하는 제2믹서, 상기 제1,2믹서의 출력신호를 각각 필터링하여 정형화하는 제1,2펄스정형 필터로 이루이진, I.Q채널신호 분리회로부와, 상기 I.Q채널신호 분리회로의 내부 발진주파수를 32분주하는 분주기와, 10MHz의 기준클럭에 의해 일정주기를 설정하여 제1레지스터, 설정된 주기동안 입력되는 분주신호를 카운트하여 상기 마이컴으로 출력하는 제2레지스터를 구비하고 입력되는, I.Q채널신호를 복조하는 Q.P.S.K 복조부를 포함하여 이루어진다.As described above, the carrier frequency error correction circuit of the satellite broadcasting reception system according to the present invention includes a microcomputer that controls the entire system, a PLL circuit unit that outputs an oscillation frequency whose error is corrected by the microcomputer, and an antenna. A low noise amplifier for receiving a signal transmitted from a satellite and amplifying a predetermined level or more, a BPF for filtering out output signals of a mixed low noise amplifier and a PLL circuit unit to remove noise of another band, and the bandpass filtered one channel A first mixer for mixing the signal and the oscillation frequency of the internal phase shifted by π / 2 phase, a second mixer for mixing the Q channel signal and the internal oscillation frequency, and a first filter for filtering and shaping the output signals of the first and second mixers, respectively. An IQ channel signal separation circuit section comprising a 2-pulse shaping filter, a divider for dividing the internal oscillation frequency of the IQ channel signal separation circuit by 32, and 10 Including a QPSK demodulator for demodulating an IQ channel signal having a first register by setting a predetermined period by a reference clock of MHz, a second register for counting the divided signal input during the set period and outputting it to the microcomputer. Is done.

Description

Carrier Frequency Error Correction Circuit of Satellite Broadcasting System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 QPSK 복조시스템의 구성블럭도. 제3도는 제1,2레지스터의 동작파형도.2 is a block diagram of a QPSK demodulation system according to the present invention. 3 is an operational waveform diagram of first and second registers.

Claims

A microcomputer that controls the entire system, a PLL circuit that outputs an oscillation frequency whose error is corrected by the control of the microcomputer, a low noise amplifier that receives a signal transmitted from the satellite through an antenna and amplifies it to a predetermined level or more, BPF for filtering out the output signal of the low noise amplifier and PLL circuit unit to remove noise of other bands, and a first mixer for mixing the bandpass filtered I-channel signal and the oscillation frequency of π / 2 phase shifted internally, Q An IQ channel signal separation circuit section comprising a second mixer for mixing a channel signal and an internal oscillation frequency, and a first and second pulse shaping filter for filtering and shaping the output signals of the first and second mixers, respectively, and the IQ channel signal separation. A divider that divides the internal oscillation frequency of the circuit by 32 and a constant period is set by the reference clock of 10 MHz to input the first register during the set period. Of the signal by counting the satellite broadcast receiving system characterized by configured by comprising: a demodulator for demodulating the Q.P.S.K I.Q channel signal that is provided to enter the second register to output to the microcomputer carrier (Carrier) The frequency error correction circuit.

2. The carrier frequency error correction circuit of claim 1, wherein the internal oscillation frequency of the I.Q channel signal separation circuit unit is controlled by the oscillation voltage of the QPSK demodulation unit via OP Amp.

※ Note: The disclosure is based on the initial application.