KR970008892A - Logic Circuit for Sensorless Motor Drive Circuit - Google Patents

Logic Circuit for Sensorless Motor Drive Circuit Download PDF

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Publication number
KR970008892A
KR970008892A KR1019950022856A KR19950022856A KR970008892A KR 970008892 A KR970008892 A KR 970008892A KR 1019950022856 A KR1019950022856 A KR 1019950022856A KR 19950022856 A KR19950022856 A KR 19950022856A KR 970008892 A KR970008892 A KR 970008892A
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KR
South Korea
Prior art keywords
signal
receiving
counter
outputs
logical
Prior art date
Application number
KR1019950022856A
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Korean (ko)
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KR0139980B1 (en
Inventor
김동훈
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김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950022856A priority Critical patent/KR0139980B1/en
Priority to JP8095175A priority patent/JPH0947077A/en
Publication of KR970008892A publication Critical patent/KR970008892A/en
Application granted granted Critical
Publication of KR0139980B1 publication Critical patent/KR0139980B1/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
    • H02P6/14—Electronic commutators
    • H02P6/16—Circuit arrangements for detecting position
    • H02P6/18—Circuit arrangements for detecting position without separate position detecting elements
    • H02P6/182—Circuit arrangements for detecting position without separate position detecting elements using back-emf in windings
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
  • Control Of Electric Motors In General (AREA)

Abstract

본 발명은 센서리스 모터 구동 회로 구현을 위한 논리 회로에 관한 것으로, 와 각각 동일하게 구성된 제1∼제3비교 수단, 제1∼제3지연 수단 및 제1∼제3선택 수단으로 구성되었으며, 카운터와 비교기를 사용하여 센서리스모터를 구동하는데 있어서, 회로를 간단하게 단일화시키고 소비 전력을 줄이도록 한 센서리스 모터 구동 회로 구현을 위한 논리 회로에 관한 것이다.The present invention relates to a logic circuit for implementing a sensorless motor driving circuit, comprising a first to a third comparison means, a first to a third delay means and a first to a third selection means, respectively, In driving a sensorless motor using a comparator and a comparator, the present invention relates to a logic circuit for implementing a sensorless motor driving circuit to simplify the circuit and reduce the power consumption.

Description

센서리스 모터 구동 회로 구현을 위한 논리 회로Logic Circuit for Sensorless Motor Drive Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 실시예에 따른 센서리스 모터 구동 회로 구현을 위한 논리회로를 나타낸 회로도이고, 제5도는 본 발명의 실시예에 따른 센서리스 모터 구동 회로 구현을 위한 논리회로에서 멀티플렉서의 상세 회로도이고, 제6도는 본 발명의 실시예에 따른 센서리스 모터 구동 회로 구현을 위한 논리회로에서 강제 기동시의 타이밍도이다.4 is a circuit diagram illustrating a logic circuit for implementing a sensorless motor driving circuit according to an embodiment of the present invention, and FIG. 5 is a detailed circuit diagram of a multiplexer in a logic circuit for implementing a sensorless motor driving circuit according to an embodiment of the present invention. 6 is a timing diagram of a forced start in a logic circuit for implementing a sensorless motor driving circuit according to an embodiment of the present invention.

Claims (4)

각각 동일하게 구성된 제1∼제3비교 수단, 제1∼제3지연 수단 및 제1∼제3선택 수단으로 이루어져 있는데, 상기 제1∼제3비교 수단은, 모터 회전시 발생하는 각 역기전압 신호를 입력받아 역기전압의 비교된 값을 출력하고, 상기 제1∼제3지연 수단은, 상기 제3선택 수단의 반전 출력, 제1선택 수단의 출력, 제2선택 수단의 출력들 각각 입력으로 받고, 클럭 신호와 리세트 신호를 각 클럭 입력과 리세트 입력으로 받으며, 카운터를 구성하여 모터의 정지시 강제 기동을 위한 논리 신호를 순차적으로 발생시키고, 상기 제1∼제3선택 수단은 상기 제1∼제3비교 수단의 출력을 각각 0입력으로 받고, 상기 제1∼제3지연 수단의 출력을 각각 1입력, 그 반전 출력을 각각 2입력으로 받으며, 역기전압 발생 신호를 각 선택 입력으로 받아, 선택 입력신호에 따라서 세개의 입력 중 하나의 입력을 선택하여 출력하고 그 반전신호를 발생시킴으로써, 각각 두개의 최종적인 논리 신호를 발생시키도록 구성되어 있는 것을 특징으로 하는 센서리스 모터 구동 회로 구현을 위한 논리 회로.Each of the first to third comparison means, the first to third delay means, and the first to third selection means, which are configured in the same manner, each of the counter electromotive voltage signals generated when the motor rotates. And output the compared value of the counter electromotive voltage, wherein the first to third delay means are respectively inputted as the inverted output of the third selecting means, the output of the first selecting means, and the outputs of the second selecting means. And receiving a clock signal and a reset signal at each clock input and reset input, and configuring a counter to sequentially generate a logic signal for forced start when the motor is stopped. Receives the outputs of the third to third comparison means as 0 inputs, receives the outputs of the first to third delay means to one input and the inverted outputs to each of the two inputs, and receives a counter electromotive voltage generation signal to each of the selected inputs. Depending on the input signal selected, three Selecting and outputting one of the inputs and generating the inverted signal, thereby generating two final logic signals, respectively. 제1항에 있어서, 상기한 제1∼제3지연 수단은, 디 플립플롭으로 이루어져 있는 것을 특징으로 하는 센서리스 모터 구동 회로 구현을 위한 논리 회로.2. The logic circuit as set forth in claim 1, wherein said first to third delay means comprise a de-flip flop. 제1항에 있어서, 상기한 제1∼제3선택 수단은, 역기전압 발생 신호를 각 선택 입력으로 받아서 선택 입력에 따라서 모터의 정지시와 모터의 회전시를 식별하는 기능을 갖는 멀티플랙서로 이루어져 있는 것을 특징으로 하는 센서리스 모터 구동 회로 구현을 위한 논리 회로.The method according to claim 1, wherein the first to third selection means comprise a multiplexer having a function of receiving a counter electromotive voltage generation signal as each selection input and discriminating when the motor is stopped and when the motor is rotated according to the selection input. Logic circuit for implementing a sensorless motor drive circuit, characterized in that. 제3항에 있어서, 상기한 멀티플렉서는, 상기 역기전압의 비교된 신호와 상기 역기전압 발생 신호를 각각 입력받아, 반전시켜 출력하는 제1, 제2인버터와; 상기 지연 수단의 출력과 상기 역기전압 발생 신호를 입력받아, 논리곱을 수행하는 제1논리곱 수단과; 상기 제1인버터의 출력과 상기 역기전압의 비교된 신호를 입력받아, 논리곱을 수행하는 제2논리곱 수단과; 상기 제1인버터와 제2인버터의 출력을 입력받아, 논리곱을 수행하는 제3논리곱 수단과; 상기 역기전압 발생 신호와 상기 지연 수단의 반전 출력을 입력받아, 논리곱을 수행하는 제4논리곱 수단과; 상기 제1, 제2논리곱 수단의 출력을 입력받아, 논리합을 수행하는 제1논리합 수단과; 상기 제3, 제4논리곱 수단의 출력을 입력받아, 논리합을 수행하는 제2논리합 수단으로 이루어져 있는 것을 특징으로 하는 센서리스 모터 구동 회로 구현을 위한 논리 회로.4. The apparatus of claim 3, wherein the multiplexer comprises: first and second inverters which receive the compared signal of the counter voltage and the counter voltage generation signal, respectively, and inverts and outputs the counter voltage; First logical multiplication means for receiving the output of the delay means and the counter electromotive voltage generation signal and performing a logical product; Second logical product means for receiving the output signal of the first inverter and the counter signal voltage and performing a logical product; Third logical multiplication means for receiving the outputs of the first and second inverters and performing a logical product; Fourth logical product means for receiving the counter voltage generation signal and the inverted output of the delay means and performing a logical product; First logical sum means for receiving an output of the first and second logical product means and performing a logical sum; And a second logical sum means for receiving the outputs of the third and fourth logical multiplication means and performing a logical sum. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950022856A 1995-07-28 1995-07-28 Senseless motor driving logic circuit KR0139980B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019950022856A KR0139980B1 (en) 1995-07-28 1995-07-28 Senseless motor driving logic circuit
JP8095175A JPH0947077A (en) 1995-07-28 1996-04-17 Logic circuit for sensorless motor driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950022856A KR0139980B1 (en) 1995-07-28 1995-07-28 Senseless motor driving logic circuit

Publications (2)

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KR970008892A true KR970008892A (en) 1997-02-24
KR0139980B1 KR0139980B1 (en) 1998-07-15

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101664693B1 (en) * 2015-05-26 2016-10-11 서강대학교산학협력단 Logic Controller of Brushless DC Motor and the method of control for driving part of Brushless DC Motor using the same
CN108682383A (en) * 2018-06-15 2018-10-19 东莞阿尔泰显示技术有限公司 A kind of the protection circuit and its control method of LED display

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KR0139980B1 (en) 1998-07-15
JPH0947077A (en) 1997-02-14

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