KR970008524A - Semiconductor Package Manufacturing Method - Google Patents

Semiconductor Package Manufacturing Method Download PDF

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Publication number
KR970008524A
KR970008524A KR1019950019584A KR19950019584A KR970008524A KR 970008524 A KR970008524 A KR 970008524A KR 1019950019584 A KR1019950019584 A KR 1019950019584A KR 19950019584 A KR19950019584 A KR 19950019584A KR 970008524 A KR970008524 A KR 970008524A
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KR
South Korea
Prior art keywords
heat sink
solder
semiconductor chip
semiconductor package
lead
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KR1019950019584A
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Korean (ko)
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KR100192226B1 (en
Inventor
신원선
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황인길
아남산업 주식회사
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Priority to KR1019950019584A priority Critical patent/KR100192226B1/en
Publication of KR970008524A publication Critical patent/KR970008524A/en
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Publication of KR100192226B1 publication Critical patent/KR100192226B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

본 발명은 반도체 패키지 제조방법에 관한 것으로, 특히 솔더를 이용하여 히트 싱크를 반도체 칩에 접착시키는 방법에 관한 것으로, 이를 위한 본 발명은 히트싱크상에 소정두께의 솔도를 플레이팅 시킨후 반도체 칩을 안착시킨 후 솔더 리플로우를 통해 히트싱크상에 반도체 칩을 접착시키거나, 반도체 웨이퍼 뒷면에 솔더 플레이팅을 한 후 소잉하여 개별 반도체 칩으로 분리시킨 후 히트싱크상에 안착시키고 솔더 리플로우를 통해서 반도체 칩을 히트싱크에 접착시키게 된다.The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a method of bonding a heat sink to a semiconductor chip by using a solder. The present invention provides a semiconductor chip after plating a predetermined thickness of a brush on a heat sink. After attaching the semiconductor chip on the heat sink through solder reflow, or solder plating on the back side of the semiconductor wafer, sawing and separating it into individual semiconductor chips, it is deposited on the heat sink and through solder reflow The semiconductor chip is bonded to the heat sink.

Description

반도체 페키지 제조방법Semiconductor Package Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도의 (A) 내지 (C)는 본 발명의 제1실시예를 도시한 단면도, 제4도의 (A) 내지 (C)는 본 발명의 제2실시예를 도시한 단면도, 제5도의 (A) 내지 (C)는 본 발명의 제3실시예를 도시한 단면도.3A to 3C are cross-sectional views showing the first embodiment of the present invention, and FIGS. 4A to 4C are cross-sectional views showing the second embodiment of the present invention, and FIG. A) to (C) are sectional views showing a third embodiment of the present invention.

Claims (9)

히트싱크를 반도체 패키지에 내장하여 사용하는 반도체 패키지 제조방법에 있어서, 히트싱크상에 솔더를 소정두께로 플레이팅하는 단계와, 상기 솔더 플레이팅된 히트싱크의 상면 주변에 접착물질을 통해서 리드프레임의 리드를 접착시키는 단계와, 상기 솔더 플레이팅된 히트싱크의 중앙에 반도체 칩을 안착시키는 단계와, 상기 반도체 칩이 안착된 히트싱크를 솔더 리플로우 하므로 반도체 칩이 히트싱크 상면에 접착되게 하는 단계를 포함함을 특징으로 하는 반도체 패키지 제조방법.A method of manufacturing a semiconductor package in which a heat sink is embedded in a semiconductor package, the method comprising: plating a solder to a predetermined thickness on a heat sink, and forming a lead frame through an adhesive material around an upper surface of the solder plated heat sink. Adhering a lead, depositing a semiconductor chip in the center of the solder plated heat sink, and solder reflowing the heat sink on which the semiconductor chip is seated so that the semiconductor chip is bonded to an upper surface of the heat sink. A semiconductor package manufacturing method comprising the. 제1항에 있어서, 상기 리드 내측의 히트싱크와 리드의 접착 물질상에는 솔더 리플로우시 솔더 오버플로우 방지 가이드링이 리드와 격리되어 형성되는 것을 특징으로 하는 반도체 패키지 제조방법.The method of claim 1, wherein a solder overflow preventing guide ring is formed on the heat sink inside the lead and the adhesive material of the lead when the solder reflow is isolated from the lead. 제1항 또는 2항에 있어서, 상기 히트싱크상의 솔더 플레이팅 두께는 약 300마이크로 인치인 것을 특징으로 하는 반도체 패키지 제조방법.The method of claim 1 or 2, wherein the thickness of the solder plating on the heat sink is about 300 micro inches. 히트싱크를 반도체 패키지에 내장하여 사용하는 반도체 패키지 제조방법에 있어서, 히트싱크상에 솔더를 소정두께로 플레이팅하는 단계와, 리드프레임의 내부리드내에 솔더 오버플로우 방지용 가이드링을 형성하는 단계와, 상기 솔더 플레이팅된 히트싱크상에 반도체 칩 및 가이드링을 안착시키는 단계와, 상기 반도체 칩 및 가이드링이 안착된 히트싱크를 솔더 리플로우 하므로 반도체 칩 및 가이드링이 히트싱크 상면에 접착되게 하는 단계를 포함함을 특징으로 하는 반도체 패키지 제조방법.A semiconductor package manufacturing method using a heat sink embedded in a semiconductor package, comprising the steps of: plating a solder to a predetermined thickness on a heat sink; forming a guide ring for preventing solder overflow in an inner lead of the lead frame; Mounting the semiconductor chip and the guide ring on the solder plated heat sink, and soldering the semiconductor chip and the guide ring to the heat sink on which the semiconductor chip and guide ring are seated so that the semiconductor chip and the guide ring are adhered to the upper surface of the heat sink. Semiconductor package manufacturing method comprising a. 제4항에 있어서, 상기 히트싱크의 솔더 플레이팅 두께는 약 300마이크로 인치인 것을 특징으로 하는 반도체 패키지 제조방법.5. The method of claim 4, wherein the solder plating thickness of the heat sink is about 300 micro inches. 히트싱크를 반도체 패키지에 내장하여 사용하는 반도체 패키지 제조방법에 있어서, 히트싱크상에 소정크기 및 깊이의 리세스 웰(Recess Well)을 형성하는 단계와, 상기 히트싱크의 리세스 웰에 웰 깊이를 넘지 않게 솔더를 플레이팅하는 단계와, 상기 히드싱크의 변두리에 접착물질을 통해 리드프레임의 리드를 접착시키는 단계와, 상기 히트싱크의 리세스 웰에 반도체 칩을 안착시키는 단계와, 상기 반도체 칩이 안착된 히트싱크를 솔더 리플로우하므로 반도체 칩을 히트싱크에 접착시키는 단계를 포함함을 특징으로 하는 반도체 패키지 제조방법.A method of manufacturing a semiconductor package in which a heat sink is embedded in a semiconductor package, the method comprising: forming a recess well having a predetermined size and depth on the heat sink, and forming a well depth in a recess well of the heat sink. Plating the solder so as not to exceed, adhering the lead of the leadframe to the edge of the heat sink through an adhesive material, and depositing the semiconductor chip in the recess well of the heat sink, And soldering the seated heat sink to solder reflow, thereby bonding the semiconductor chip to the heat sink. 제6항에 있어서, 상기 리세스 웰의 깊이는 300마이크로 인치보다 깊은 것을 특징으로 하는 반도체 패키지 제조방법.7. The method of claim 6, wherein the depth of the recess well is greater than 300 micro inches. 히트싱크를 반도체 패키지에 내장하여 사용하는 반도체 패키지 제조방법에 있어서, 반도체 웨이퍼의 뒷면에 소정두께로 솔더를 플레이팅 하여 경화시킨 후 소잉(Sawing)하는 단계와, 히트싱크의 주변부 상에 접착물질을 통해서 리드프레임의 리드를 접착시키는 단계와 상기 히트싱크 상부의 중앙에 상기 반도체 칩을 안착시키는 단계와, 상기 반도체 칩이 안착된 히트싱트를 솔더 리플로우 하므로 반도체 칩과 히트싱크를 부착시키는 단계를 포함함을 특징으로 하는 반도체 패키지 제조방법.A semiconductor package manufacturing method using a heat sink embedded in a semiconductor package, comprising the steps of: plating a hardened solder to a predetermined thickness on a back surface of a semiconductor wafer, and then sawing the adhesive material on a periphery of the heat sink; Adhering a lead of a lead frame through the lead frame; and mounting the semiconductor chip at the center of the heat sink, and attaching the semiconductor chip and the heat sink to each other by solder reflowing the heat sink on which the semiconductor chip is seated. Method of manufacturing a semiconductor package, characterized in that. 제8항에 있어서, 상기 반도체 칩 뒷면의 솔더 플레이팅 두께는 약 300마이크로 인치인 것을 특징으로 하는 반도체 패키지 제조방법.9. The method of claim 8 wherein the thickness of the solder plating on the backside of the semiconductor chip is about 300 micro inches. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019584A 1995-07-05 1995-07-05 Method for manufacturing semiconductor package KR100192226B1 (en)

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KR1019950019584A KR100192226B1 (en) 1995-07-05 1995-07-05 Method for manufacturing semiconductor package

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KR1019950019584A KR100192226B1 (en) 1995-07-05 1995-07-05 Method for manufacturing semiconductor package

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KR970008524A true KR970008524A (en) 1997-02-24
KR100192226B1 KR100192226B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724587B1 (en) * 2006-12-12 2007-06-04 (주)파워벨리 Device for both solder die bonding and epoxy die bonding and method for die bonding using the device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724587B1 (en) * 2006-12-12 2007-06-04 (주)파워벨리 Device for both solder die bonding and epoxy die bonding and method for die bonding using the device

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KR100192226B1 (en) 1999-06-15

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