KR970007874B1 - 4차 시그마 델타(σδ) 변조기 - Google Patents
4차 시그마 델타(σδ) 변조기 Download PDFInfo
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- KR970007874B1 KR970007874B1 KR1019940020531A KR19940020531A KR970007874B1 KR 970007874 B1 KR970007874 B1 KR 970007874B1 KR 1019940020531 A KR1019940020531 A KR 1019940020531A KR 19940020531 A KR19940020531 A KR 19940020531A KR 970007874 B1 KR970007874 B1 KR 970007874B1
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Abstract
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Claims (1)
- 샘플링 주기가 T일때, 입력신호(X(Z))를 입력받아 계수화하고, T/2 만큼 지연시키는 4개의 피드포워드 계수수단(45 내지 48) ; 출력신호(Y(Z))를 계수화하고, T/2만큼 지연시키는 4개의 피드백 계수수단(49 내지 52) ; 상기 피드포워드 계수수단(45 내지 48)과 피드백 계수수단(49 내지 52)중 각각 하나씩의 계수수단의 출력 차와 전단의 적분값의 합을 각각 입력받는 직렬구조이되, 최하위를 제외한 나머지는 T/2 만큼의 지연시간을 가지며 적분하는 4개의 적분수단(41 내지 44)을 구비하는 4차 시그마 델타 변조기에 있어서, 상기 계수부(45 내지 48) 각각에 입력되는 입력신호(X(Z))를 T/2 만큼 지연시키는 입력신호 지연수단(61) ; 상기 입력신호 지연수단(61)의 출력을 특정 시간 지연없이 계수화하는 양자화 피드포워드 계수수단(62) ; 출력신호(Y(Z))를 특정 시간 지연없이 계수화하는 양자화 피드백 계수수단(63) ; 및 상기 양자화 피드포워드/피드백 계수수단(62, 63)의 출력 차와 최하위 적분수단(44)의 출력을 동시에 양자화하는 양자화수단(300)을 구비하는 것을 특징으로 하는 4차 시그마 델타 변조기.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940020531A KR970007874B1 (ko) | 1994-08-19 | 1994-08-19 | 4차 시그마 델타(σδ) 변조기 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940020531A KR970007874B1 (ko) | 1994-08-19 | 1994-08-19 | 4차 시그마 델타(σδ) 변조기 |
Publications (1)
Publication Number | Publication Date |
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KR970007874B1 true KR970007874B1 (ko) | 1997-05-17 |
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Application Number | Title | Priority Date | Filing Date |
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KR1019940020531A Expired - Fee Related KR970007874B1 (ko) | 1994-08-19 | 1994-08-19 | 4차 시그마 델타(σδ) 변조기 |
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KR (1) | KR970007874B1 (ko) |
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1994
- 1994-08-19 KR KR1019940020531A patent/KR970007874B1/ko not_active Expired - Fee Related
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