KR970006022B1 - Product code circuit using eraser - Google Patents

Abstract

Product code circuit using the eraser, where product the lots of error according to detecting the error of the column and row direction in the product code. The said circuit checks the used code word of the column and row vector of the symbol in order to encode, and consists of a eraser generating means that makes the symbol to the eraser using the error detecting means.

Description

Circuit Code Circuit Using Eraser

1 is a diagram showing the structure of a conventional network code.

2 is a block diagram showing a conventional error correction circuit.

3 is a diagram showing the structure of a network code according to the present invention.

4 is a block diagram of an error correction circuit using an erasure according to a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

401 and 403: error detector 405: erasure generator

407, 409: error-erase correction decoder

The present invention relates to a circuit code (Product Code) circuit using an eraser, and more particularly to the error of the line, column code by erasing as many errors as possible by error detection in the row and column direction in the network code The present invention relates to a circuit code circuit using an erasure to increase the correction capability.

1 is a diagram showing a structure of a conventional network code, in which kxm information symbols are added with (1xn)-(kxm) parity to generate a code for error correction. That is, according to the structure of the conventional network code, the coding is performed in the row direction using the (n, k) code and the coding is performed in the column direction using the (1, m) code.

2 is a block diagram showing a conventional error correction circuit that performs the network encoding as described above. As shown in the same figure, the (n, k) error correction decoding unit 201 and (1, m) error correction decoding are shown. Section 203. Often, the error correction circuit of this structure performs error correction decoding in the (n, k) row direction through the (n, k) error correction decoding unit 201, and then again (1, m) error correction decoding unit ( In step 203, error correction decoding in the (1, m) column direction is performed.

Therefore, in the prior art, the decoding performance in the row direction and the column direction, that is, the two decoding operations, for one information symbol shows good decoding performance.

However, as is well known in the art, in view of the fact that at the same code rate, error erasure correction decoding can allow a larger number of corrections than error correction decoding, the prior art as described above is applied to one information symbol. Since error correction is performed for each row and column, the error correction capability is lower than that of error-erase correction decoding at the same code rate.

The present invention is to solve the problems of the prior art as described above, by performing an error detection in the row and column, and then by erasing the symbol having a very high probability of error to be an erasure that can perform an efficient error correction The purpose is to provide the network code circuit used.

In order to achieve the above object, the present invention checks whether the vector of the given row and column direction of a given symbol is a code word used for incubation, and determines that there is no error if it is a code word. Erasure generating means for erasing the predetermined symbol when the error detection means detects an error in a predetermined row and column vector at the same time by using error detecting means for detecting errors in the row and column directions; Provided is a network encoding circuit using an erasure consisting of error erasure correction decoding means for correcting a row eraser and a column eraser respectively from the eraser generating means.

Hereinafter, a preferred embodiment of a network code circuit using an erasure according to the present invention will be described in detail with reference to the accompanying drawings.

3 shows a structure of a network code according to the present invention. As shown in the same drawing, in the embodiment of the present invention, k × m information symbols are represented by (1 × n)-(k × m) parity. In addition, make a code for error correction, and assume that the row vector H and the column vector V are given, and the symbol C has an error.

4 is a block diagram of a network code circuit using an erasure according to the present invention. As shown in the figure, the circuit code circuit of the present invention includes (n, k) error correction detector 401, (1, m) error correction detector 403, erasure generator 405, (n, k) an error erasure correction decoding unit 407 and a (1, m) error erasure correction decoding unit 409.

In FIG. 4, the (n, k) error detecting unit 401 determines whether the vector in the given row direction is a code word used for encoding, and determines that there is no error if the code word is used. The error detection unit 403 determines that there is no error if the vector in the given column direction is a code word, and determines that an error has occurred if it is not a code word.

On the other hand, the erasure generator 405 determines whether or not the symbol is erased based on the error detection results from the (n, k) and (1, m) error detection units 401, 403. In other words, if an error is detected at the same time in the row direction and the column direction of the given symbol, the erasure generator 405 erases the corresponding symbol.

On the other hand, the (n, k) error erasure correction decoding unit 407 and the (1, m) error erasure correction decoding unit 409 are connected in series to the eraser generation unit 405 described above. Errors are sequentially corrected in the row direction and the column direction with respect to the eraser of the symbol.

Next, the operation of the error correction decoder of the present invention having the above configuration will be described in detail.

First, when an encoded signal is input, an error (n, k) is detected in the row direction of the corresponding symbol through the (n, k) error detector 401 and at the same time, the corresponding error is detected through the (1, m) error detector 403. A (1, m) error is detected in the column direction of the symbol.

Here, the error detection is determined based on whether or not a given row or column vector is a code word used for encoding, and if it is a code word, it is determined that there is no error. It seems to be.

On the other hand, the erasure generator 405 is a symbol based on the occurrence of errors in the row and column directions detected by the (n, k) error detectors 401 and (1, m) error detectors 403 described above. Determine whether the eraser is generated.

That is, if an error is detected in the row vector H of a given symbol and an error is detected in the column vector V, the symbol C is determined to be an error, and the symbol C is made into an eraser by the erasure generator 405.

Here, the erasure means a value that is considered to have an error in the symbol, but is left without specifying any value because the exact error value is not known.

Then, the eraser of the predetermined symbol according to the occurrence of the error of the row and column generated by the eraser generator 405 is (n, k) through the error eraser correction decoder 407 in the row direction. The erasure is corrected, and the error is corrected by sequentially correcting the error-erasure in the column direction through the (1, m) error erasure correction decoder 409.

In practice, the erasure correction as described above requires less parity than error correction, resulting in much better performance than error correction.

As described above, according to the present invention, error correction is performed by detecting an error in a row and a column of a given vector and then erasing a symbol having a very high probability of error, that is, a symbol in which the error is detected in both the row and the column. As an effect, the correction ability of the destination code is effectively enhanced as compared with the above-described prior art.

In addition, since the error detection according to the present invention is only to determine whether the code word or not, it is not necessary to use a separate parity, so that a good performance can be obtained only by changing the decoder without changing the conventional encoding. There is.

Claims (1)

Erasure generating means for erasing the predetermined symbol when an error occurs simultaneously in a predetermined row and column vector in the error detecting means; And an erasure code circuit comprising error erasure correction decoding means for correcting the eraser in the row direction and the eraser in the column direction from the eraser generating means.