KR970004809A - Error discrimination circuit - Google Patents

Error discrimination circuit Download PDF

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Publication number
KR970004809A
KR970004809A KR1019950018783A KR19950018783A KR970004809A KR 970004809 A KR970004809 A KR 970004809A KR 1019950018783 A KR1019950018783 A KR 1019950018783A KR 19950018783 A KR19950018783 A KR 19950018783A KR 970004809 A KR970004809 A KR 970004809A
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KR
South Korea
Prior art keywords
signal
absolute value
error
circuit
phase
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KR1019950018783A
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Korean (ko)
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KR0175725B1 (en
Inventor
최형수
전경훈
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김주용
현대전자산업 주식회사
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Priority to KR1019950018783A priority Critical patent/KR0175725B1/en
Publication of KR970004809A publication Critical patent/KR970004809A/en
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Publication of KR0175725B1 publication Critical patent/KR0175725B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Error Detection And Correction (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

본 발명은 알고리듬 전개상 나눗셈없이 간단한 로직연산만을 이용하여 위상오차와 이득오차를 구하는 오차 판별 회로에관한 것이다.The present invention relates to an error discrimination circuit that obtains a phase error and a gain error using only a simple logic operation without division in algorithm development.

디지탈 신호 처리시 위상오차와 이득오차를 추적하여 보상하는 위상 추적루프에 이용되는 오차 판별 회로에 있어서, 이득오차 g=(│↑│-│1"│)(여기서 1"는 오차 판별 회로 입력신호의 동위상 신호, ↑는 1"로부터 판정된 신호임)를 구하기 위해, 상기 오차 판별 회로 입력신호의 동위상 신호(1")의 절대치를 구하는 절대치 회로와, 상기 절대치 회로로부터 구해진 상기 동위상 신호의 절대치 신호를 양자화하는 양자화기와, 상기 양자화기로부터 출력되는 양자화신호로부터 상기 절대치 회로로부터 출력되는 상기 절대치 신호를 감산하여 이득오차를 구하는 감산기를 포함한다.In an error discrimination circuit used in a phase tracking loop for tracking and compensating for phase error and gain error during digital signal processing, gain error g = (│ ↑ │-│1 "│), where 1" is an error discriminating circuit input signal. An absolute value circuit for obtaining the absolute value of the in-phase signal 1 "of the error discrimination circuit input signal and the in-phase signal obtained from the absolute value circuit, And a subtractor for subtracting the absolute value signal output from the absolute value circuit from the quantized signal output from the quantizer to obtain a gain error.

Description

오차 판별 회로Error discrimination circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 HDTV 수신단에 사용된 종래의 위상 추적 루프도, 제2도는 본 발명에 따른 오차 판정 회로의 상세 블럭도, 제3도는 본 발명에 따라서 구하고자 하는 위상오차 phi의 그래프.1 is a conventional phase tracking loop diagram used in an HDTV receiver, FIG. 2 is a detailed block diagram of an error determination circuit according to the present invention, and FIG. 3 is a graph of phase error phi to be obtained according to the present invention.

Claims (2)

디지탈 신호 처리시 위상오차와 이득오차를 추적하여 보상하는 위상 추적루프에 이용되는 오차 판별 회로에 있어서, 이득오차 g=(│↑│-│1"│)(여기서 1"는 오차 판별 회로 입력신호의 동위상 신호, ↑는 1"로부터 판정된 신호임)를 구하기 위해, 상기 오차 판별 회로 입력신호의 동위상 신호(1")의 절대치를 구하는 절대치 회로와, 상기 절대치 회로로부터 구해진 상기 동위상 신호의 절대치 신호를 양자화하는 양자화기와, 상기 양자화기로부터 출력되는 양자화신호로부터 상기 절대치 회로로부터 출력되는 상기 절대치 신호를 감산하여 이득 오차를 구하는 감산기를 포함하는 것을 특징으로 하는 오차 판별 회로.In an error discrimination circuit used in a phase tracking loop for tracking and compensating for phase error and gain error during digital signal processing, gain error g = (│ ↑ │-│1 "│), where 1" is an error discriminating circuit input signal. An absolute value circuit for obtaining the absolute value of the in-phase signal 1 "of the error discrimination circuit input signal and the in-phase signal obtained from the absolute value circuit, And a subtractor for quantizing the absolute value signal of the quantizer, and a subtractor for obtaining a gain error by subtracting the absolute value signal output from the absolute value circuit from the quantized signal output from the quantizer. 디지탈 신호 처리시 위상오차와 이득오차를 추적하여 보상하는 위상 추적루프에 이용되는 오차 판별 회로에 있어서, 위상오차 phi=sgn(1")sgn(Q")(|↑|-|1"|)/│Q│(여기서 1"는 오차 판별 회로 입력신호의 동위상 신호, Q"는 오차 판별 회로 입력신호의 직각신호, ↑는 1"로부터 판정된 신호, Q는 …, 1/2, 1, 2, 4, 8, …임)를 구하기 위해서, 상기 오차 판별 회로 입력신호의 동위상신호(1")의 절대치를 구하는 절대치 회로와, 상기 절대치 회로로부터 구해진 상기 동위상 신호의 절대치 신호를 양자화하는 양자화기와, 상기 양자화기로부터 출력되는 양자화신호로부터 상기 절대치 회로로부터 출력되는 상기 절대치 신호를감산하여 이득오차를 구하는 감산기와, 상기 오차 판별 회로 입력신호의 직각 신호(Q")의 절대치를 구하는 절대치 회로와,상기 직각 신호의 절대치의 정수부분을 취하기 위해 1/2, 1, 2, 4, 8로 양자화하는 정수화 회로와, 상기 정수화 회로로부터 출력된 양자화신호의 우선순위를 지정하는 우선순위 인코더와, 상기 오차 판별 회로 입력신호의 동위상 신호와 직각위상 신호의 부호비트를 연산하는 부호비트 연산회로와, 상기 연산된 부호비트를 EX-OR논리연산하는 EX-OR게이트와, 상기감산기로부터 출력된 이득오차를 상기 우선순위 인코더의 출력만큼 k-비트 시프트 라이트시키는 시프트 연산회로와, 상기시프트 연산회로의 출력을 2의 보수로 만드는 NEGATE, 및 상기 우선순위 인코더의 출력만큼 k-비트 시프트 라이트된 결과를 상기 부호비트를 EX-OR논리연산된 신호에 따라 그대로 또는 반전시키는 MUX를 포함하는 것을 특징으로 하는 오차 판별회로.An error discrimination circuit used in a phase tracking loop that tracks and compensates for phase and gain errors in digital signal processing, wherein the phase error phi = sgn (1 ") sgn (Q") (| ↑ |-| 1 "|) (Where 1 "is an in-phase signal of the error discriminating circuit input signal, Q" is a right angle signal of the error discriminating circuit input signal, ↑ is a signal determined from 1 ", Q is ..., 1/2, 1, 2, 4, 8, ...) to quantize the absolute value circuit for obtaining the absolute value of the in-phase signal 1 "of the error discriminating circuit input signal and the absolute value signal of the in-phase signal obtained from the absolute value circuit. A quantizer, a subtractor for subtracting the absolute value signal output from the absolute value circuit from the quantized signal output from the quantizer to obtain a gain error, and an absolute value circuit for obtaining the absolute value of the quadrature signal Q " And absolute value of the quadrature signal. An integerization circuit that quantizes 1/2, 1, 2, 4, 8 to take an integer part, a priority encoder that specifies the priority of the quantized signal output from the integerization circuit, and the error discrimination circuit input signal. A code bit calculation circuit for calculating code bits of a phase signal and a quadrature phase signal, an EX-OR gate for performing EX-OR logic operation on the calculated code bits, and a gain error output from the subtractor to output the priority encoder. A shift operation circuit for k-bit shift writes by N, a NEGATE for making the output of the shift operation circuits two's complement, and a result of k-bit shift writes as much as the output of the priority encoder. And an MUX for inverting or inverting according to the calculated signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950018783A 1995-06-30 1995-06-30 Error detecting circuit KR0175725B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950018783A KR0175725B1 (en) 1995-06-30 1995-06-30 Error detecting circuit

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Application Number Priority Date Filing Date Title
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KR970004809A true KR970004809A (en) 1997-01-29
KR0175725B1 KR0175725B1 (en) 1999-05-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429859B1 (en) * 1997-05-22 2004-06-16 삼성전자주식회사 Method and apparatus for determining expanding region in electronic zoom system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429859B1 (en) * 1997-05-22 2004-06-16 삼성전자주식회사 Method and apparatus for determining expanding region in electronic zoom system

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