KR930008434B1 - Code output and data multiplexing method - Google Patents

Abstract

The data multiplexing method includes the steps of: generating more than one reference value in response to a reference value input to a reference input port; comparing the plurality of reference values generated from the reference value generating step and a signal input to a first input port, quantizing the compared result, and coding it in predetermined bits; and generating more than one multiplication factor in response to a signal input to a second input port and selecting at least one multiplication factor among the generated multiplication factors by the code generated from the code generating step, thereby reducing hardware and increasing the operation processing speed.

Description

Method and apparatus for multiplexing data by code generation

1 is a block diagram of a conventional multiplier.

2 is a block diagram of a code generation and multiplexing apparatus according to the present invention.

3 is an input / output characteristic diagram according to FIG.

4 is a detailed circuit diagram of the multiplication selector according to FIG.

5 is a circuit diagram of one embodiment of the present invention.

6 is a circuit diagram of one embodiment of a horizontal contour correction device applied to the present invention.

* Explanation of symbols for main parts of the drawings

10: reference generator 20: code generator

30: multiplication selector

The present invention relates to a method and a device for data multiplexing caused by code generation. In particular, in the case of receiving and calculating two input signals, the outputs are multiplied by two input signals without using a multiplier. The present invention relates to a method and apparatus for data multiplexing by code generation.

In general, multipliers are widely used in image processing systems for digitalizing and processing image signals. For example, they are widely used in amplifiers or attenuators, phase detectors, demodulators, and the like of analog circuits in digital image processing systems. Examples of circuits for performing multiplication operations using multipliers such as those described above in televisions include gain control of horizontal and vertical contour compensation, contrast control and brightness control, and color. Essentially used for demodulation circuits. The multiplier used in such a circuit is composed of a large number of hardware, which has a problem that is accompanied by various restrictions, and the situation is required to solve such a problem.

1 is a block diagram of a conventional multiplier, which shows an example of an array type configuration. 1A is an overall configuration diagram of an array cell of 4x4 bits, and (1b) is an internal detailed view of the multiplier M corresponding to each cell of the multipliers of (1a). Referring to FIG. 1B, it can be seen that the cells illustrated in FIG. 1A, that is, one multiplier M, are each composed of one end gate 1 and a full adder 2. . When the multiplication operation of 4x4 bits is performed by using the multiplier M configured as the 1b diagram, a total of 16 are required as the 1a diagram, which is a cell configured as the 1b diagram.

In FIG. 1A, when the input terminal X0-X3 is a multiplier and the input terminal Y0-Y3 is a multiplier, the output of the output terminals S0-S7 is an output multiplied by the multiplier and the multiplier. That is, the internal operation of the array multiplier configured as shown in FIG. 1a performs an iteration of addition and outputs the result as multiplied. For example, when a binary number "10" is called a multiplier and a binary number "1111" is a multiplier, the multiplication operation of the multiplier and the multiplier is as follows.

In the above step 1, since the least significant bit of the multiplier is "1", the multiplicand "10" is displayed at the positions of the output terminals S0-S3. In step 2, since the multiplier bit (terminal of Y1) after step 1 is "1", the multiplicand "10" is displayed at the positions of output terminals S1-S4 and addition with the output "10" of step 1 is performed. do. Further, in step 3, the multiplier bit following the step 2 (the input terminal of Y2) is "1", so the multiplicand "10" to be input is displayed at the position of S2-S5 and the result is added to the result calculated in step 2. . When the above operation is completed, the multiplier bit after the third step, that is, the best bit is "1" in step 4, so the multiplicand "10" is displayed at the position S3-S6, and the addition with step 3 performs "11110". Will output the value of "."

Therefore, the conventional multiplier configured as shown in the first diagram performs four additions and shift-left as described above, thereby outputting the final output "11110". However, when the multiplier is " 0 ", only the shift is made and no addition is made. Therefore, in the conventional multiplier as described above, in order to multiply the multiplier by inputting the multiplier, an operation processing time for adding the multiplier by the number of bits of the multiplier is required, and the operation processing time increases with the number of input bits. You can see. The multiplier having the above configuration increases the number of cells of the multiplier as the number of input bits increases. That is, when performing 8x8 bit operation, 64 cells of the multiplier M are required, which increases the processing time.

Therefore, conventionally, when multiplying two input signals and performing multiplication, the multiplier operates as a multiplier. Therefore, there is a problem in that the amount of hardware is increased. In addition, it is well known that the above disadvantages not only cause a lot of problems in the design of the system, but also adversely affect the cost.

Accordingly, an object of the present invention is to provide a method and apparatus for data multiplexing by code generation which can obtain the same output as multiplying two input signals without using a multiplier in view of the above problems.

Another object of the present invention is to provide a method and apparatus for data multiplexing by code generation that can quantize one input by comparing a predetermined reference value.

Another object of the present invention is to provide a method and apparatus for data multiplexing by code generation which can reduce the burden of hardware without using a multiplier.

Another object of the present invention is to provide a method and apparatus for data multiplexing by code generation, which can increase arithmetic processing speed compared to using a multiplier.

Another object of the present invention is to provide a method and apparatus for data multiplexing by code generation which can be applied to a horizontal contour compensation circuit of an image signal processing apparatus.

In order to achieve the above objects, the present invention is characterized in that one input of two input signals is compared with a reference value, quantized, and then coded, and the other input is selected and output.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a code generation and multiplexing apparatus according to the present invention, which includes a reference generator 10 generating at least one reference value in response to a reference value input to a reference input terminal Ref, and a first input terminal. A code generator 20 for outputting the signal inputted to (A) and the output of the reference generator 10 and outputting the output signal to the output terminal D by encoding a predetermined bit and outputting it to the output terminal D, and the code generator ( A multiplication selector 30 which selects a multiplication factor of an input signal input to the second input terminal B and outputs the selected output terminal C according to the code of the output terminal D of FIG. do.

3 shows an input / output characteristic diagram according to the present invention. In FIG. 3, the horizontal axis represents an input and the vertical axis represents an output. Here, N is an integer not including "0", B means a signal input to the second input terminal (B).

FIG. 4 is a detailed circuit diagram of the multiplication selector 30 according to FIG. 2, wherein at least one multiplication factor of the multiplication factors 30a-30n of the input signal input to the second input terminal B is generated. And selecting means for selecting by the output code of the output terminal D of the section 20 and outputting the selected output terminal C.

5 is a circuit diagram of an embodiment of the present invention, which includes a reference generator 10, a code generator 20, and a multiply selector 30. The second reference numeral and the same reference numeral are used. FIG. 5 illustrates an embodiment in which N = 2, that is, generating 2N reference values.

6 is a circuit diagram of an embodiment of a horizontal contour correction device applied to the present invention, the first derivative 2 which is differentiated to input an input image signal S1 to clarify the outline of an image, and the first derivative. Boost the low level signal difference component by inputting the output of the second derivative 4 for inputting the output of the second part and outputting the second differential signal in which the high frequency component is emphasized. A booster section 6, an absolute value section 8 for inputting the output of the first derivative section 2, and taking an absolute value with a predetermined time difference, and a predetermined time difference between the absolute section section 8 and A reshape unit 9 for outputting data before or after the edges are detected by comparing the outputs with each other, and a delay unit 1 for delaying a predetermined time to horizontally compensate the input image signal S1; , The reference value of the booster unit 6, the output and the reference generator 10 A code generation unit 20 for comparing the coded output with a predetermined bit, a multiplication selector 30 for selecting and outputting the output data of the reshape unit 9 according to the output of the code generation unit 20, and the multiplication And an adder 50 that adds the output of the selector 30 and the delayed output of the delay unit 1 to output a horizontal contour-compensated video signal.

Hereinafter, the present invention will be described in detail with reference to FIGS. 2 to 6 based on the above-described configuration.

First, in FIG. 2, the reference generator 10 generates a plurality of reference values input to the reference input terminal Ref and inputs the reference values to the code generator 20. The code generator 20 compares and quantizes the input signal input to the first input terminal A and the output of the constant reference generator 10, multiplies it by a predetermined bit, and multiplies it through the output terminal D. Output to the selector 30.

The multiplication selector 30 selects and outputs one of the signals input to the second input terminal B, that is, one of a plurality of multiplication factors by an output code output from the code generator 20. Here, the selection output terminal C of the multiplication selector 30 is an output such that the signals input to the first input terminal A and the second input terminal B are respectively multiplied with each other. 3 is shown.

That is, the code generator 20 has a multiplier value input to the first input terminal A and 2N generated by the reference generator 10 (where "N" is an integer not including "0"). The reference values are compared with each other, and the resultant signal is output as a code of a predetermined bit through the output terminal D. Here, when the number of bits of the predetermined bit is M bits, the M is determined to be a value satisfying the following equation.

M ≧ 3.3 log (2N + 1)... … … … … … … … … … … … … … … … (One)

Since the reference generator 10 generates a reference value having N positive values and a reference value having N negative values, the reference signal input to the reference input terminal Ref is 2N. Here, the unit step of the 2N reference values is 1 / N. Therefore, the code generator 20 compares 2N reference values of the reference generator 10 with the input of the first input terminal A and generates a corresponding code.

The code is generated in the code generator 20 and is as shown in Table 1 below.

TABLE 1

In the multiplication selector 30, the code shown in Table 1 indicates that the value indicated by B is 1 / N × m [m is an integer not including “0” and has a range of −N <m <N.]. Select and output a multiply factor with weight. The detailed configuration of the multiplication selector 30 is shown as a fourth degree. In FIG. 4, the input of the second input terminal B is output in the multiplication selector 30 with a weight of 1 / N × m as shown in Table 1 above. In this case, the multiplication selector 30 selects one of the multiplication factors 30a-30n by the output code of the output terminal D of the code generator 20 and outputs the selected output terminal C.

Therefore, when the input of the second input terminal B is called a multiplier and the input of the first input terminal A is a multiplier, an output equal to the product of the multiplier and the multiplier is output to the selection output terminal C. In addition, since the multiplier is coded with M bits, it can be said that it is quantized. That is, it is evident that the processing speed of the operation and the reduction of hardware are shown when comparing the Figs. 2 and 4 with conventional multipliers.

In the following, the embodiment of the present invention will be described in detail with reference to FIG. 5, where N is "2".

First, in the case of N = 2, the reference generation unit 10 generates 2N, that is, 2 × 2 = 4, reference values as described in FIG. When 8-bit data is deposited on the first input terminal A in such a state, it is delayed by a predetermined time by the 8-bit delay unit 20a and latched out.

At this time, the 8-bit delay unit 10a of the reference generator 10 inputs 6 bits and 2 bits input to the reference input terminal Ref to latch and output 8 bits by a data latch clock (not shown). Then, the exclusive oragate 10b receives the most significant bit by inputting the most significant bit (MSB) among the output of the 8-bit delayer 10a and the delayed output of the 8-bit delayer 20a. The 8-bit adder 10c adds the output of the exclusive oragate 10b and the MSB at all times and outputs the output to the 8-bit delay 10d. The 8-bit delay unit 10d latches the output of the 8-bit adder 10c, outputs the code to the code generator 20, and outputs the half-life 10e. Therefore, four reference values of the reference generation unit 10 are output, that is, Ref, 1 / 2Ref, -1 / 2Ref, -Ref. The four reference values generated as described above are output to the code generator 20.

The 8-bit delay 20b in the code generator 20 latches the output of the 8-bit delay 20a and outputs it to the input terminal A of the 1-2 comparator 20c-20d. The three MSBs are output to a 3-bit latch 20e. Here, the output of the 8-bit delay unit 10d of the reference generator 10 and the output of the half-life 10e are respectively input to the input terminals B of the first and second comparators 20c-20d. At this time, each of the first and second comparators 20c-20d compares the signals input to the two input terminals and outputs the result as a logic signal.

Therefore, the inputs of the input terminals l, m, and n of the 3-bit latch 20e are respectively 1-bit inputs. That is, the input of the input terminal 1 is MSB of the input data of the first input terminal A, the input of the input terminal m is the output data of the first comparator 20C, and the input terminal An input of (n) is output data of the second comparator 20d. The 3-bit latch 20e latches the input data of the input terminals l, m and n to the output terminals l, md and nd. In addition, the exclusive logic gate 20f inputs the output of the output terminal I and the output of the output terminal nd, and outputs the corresponding logic output to the output terminal p. The outputs of the output terminals l, md, and p are input to the selection terminals X, y, and G of the multiplexer 30h located in the multiply selector 30. This is shown in Table 2 in detail using a table.

TABLE 2

Meanwhile, multiplicative data input to the second input terminal B of the multiply selector 30 is latched into the 8-bit delay unit 30a and input into the 8-bit latch 30b. The signal output from the output terminal Q of the 8-bit latch 30b is input to the 8-bit delay unit 30d, and the output terminal Is output to the 8-bit adder 30c. Therefore, it is input to the 8ft adder. At this time, the output of the 8-bit delay (30d, 30e) is input to the half-life (30f, 30g), respectively, LSB is discarded.

The output of the 8-bit delayer 30d is input to the input terminal 11 and the half-life 30f of the multiplexer 30h, and the output of the 8-bit delayer 30e is the input terminal of the multiplexer 30h. And half-life (30g). In this case, the half-lifes 30f and 30g each half-input the input signal into a half signal, so that the multiplexer 30h hysteresis to the second input terminal 10 (01), so that the multiplexer 30h is At least four multicept factors are input in response to one multiplicand input input to the second input terminal B. FIG. The multiplexer 30h for inputting the signals to the plurality of input terminals, respectively, selects one of the input terminals 11, 10, 01, and 00 according to a selection code input to the selection terminals X, Y, and G. Select and print.

The output of the multiplexer 30h is the result of multiplying the multiplier and the multiplicand, which are latched by the 8-bit delay unit 30i and output to the select output terminal C. If this is shown in detail as a table, it is as Table 3 below.

TABLE 3

Referring to FIG. 5 comprehensively using Tables 2 and 3 as follows.

When N = 2, the reference generator 10 generates four reference values, and the input data of the first input terminal A of the code generator 20 corresponds to four reference values of the reference generator 10. The code shown in Table 2 is generated in comparison with the reference value. Here, the code is a 3-bit code, and l, md, and p in Table 2 correspond to X, Y, and G in Table 3. Also, the code p is the exclusive logical sum of l and md.

On the other hand, the multiplication selector 30 is input to the second input terminal (B), the data called multiplier to generate 2N or 2 × 2 = 4 multiplication factor (multiplication factor). The multiplication factor generated as described above is selected by the code already generated by the above-described code generation unit 20. Here, the items not to be overlooked are 2N + (2 × 2 = 4). Since there is one, one more multiplying factor is needed.

In the present invention, a multiplication factor corresponding to "0" was used by using an enable terminal of a 4: 1 melt tip / plexer. This comes with the hardware advantage of not having to use a 5: 1 multiplexer. As a result, the output of the selective output terminal C of the multiplication selector 30 is the output of the result of multiplying the multiplier and the multiplicand.

6 is an embodiment in which the present invention is applied to a life contour compensation device of an image processing system for processing a digital video signal, and its configuration will be described in detail with respect to the operation of the life contour floating device configured as shown in FIG. .

In FIG. 6, the associative signal S1 applied from the outside is input to the primary differential part 2 and the delay part I, respectively. The input image signal S1 input to the first differential part 2 is firstly differentiated and applied to the second differential part 4 and the absolute value part 8, respectively. The first differential signal input to the second differential unit 4 is input to the booster unit 6 as an enhanced signal of the second differential high frequency component. The absolute value unit 8 outputs the first differential signal inputted to the reshape unit 9 after being absoluteized with a predetermined time difference.

On the other hand, the subsidiary unit 6 amplifies the input differential derivative signal to a signal having a predetermined level and outputs it to the code generator 20. In this case, the code generator 20 compares the reference value generated by the reference generator 10 with the input level limit amplification value as described above with reference to FIGS. 2 to 5, and generates a corresponding code. To the multiplication selector 30.

At this time, the reshape unit 9 reshapes the absolute value signal outputted from the absolute value unit 9 and outputs the signal to the multiplication selector 30. The multiplication selector 30 generates four multiplying factors in response to the input of the reshaping output signal from the reshaping unit 9, and outputs one of the generated multiplying factors from the code generation unit 20. Select and output according to the code. The output of the multiplication selector 30 is the same signal as the multiplication of the predetermined level limited amplification value which is the output of the booster section 6 and the reshaping output value which is the output of the reshaping section 9.

The signal output from the multiplication selector 30 and the original input video signal S1 output from the delay unit 1 are added by the adder 50 and output as a horizontal contour-compensated video signal. Therefore, the horizontal contour compensating circuit required to multiply the video signal can be multiplied without using a multiplier, thereby simplifying hardware reduction and circuit design.

As described above, when the two input signals are operated, the same output can be obtained by multiplying the two inputs without using a multiplier, thereby reducing the burden on hardware and increasing the image processing speed. There is this.

Claims (3)

A code generation and data multiplexing method for obtaining an output of a result of multiplying two input signals, the method comprising: a reference generation process of generating one or more reference values different from each other at least in response to a reference value input to a reference input terminal; A code generation process of comparing a plurality of reference values generated from the process with a signal input to the first input terminal, quantizing the coded signals with predetermined bits, and outputting the coded bits with predetermined bits; and at least one multiplier in response to the signal input to the second input terminal And a multiplication selecting step of selecting and outputting at least one multiplier of the multipliers generated by the code output in the code generation process. The code generation and data multiplexing method of claim 1, wherein the code generation process generates a code M satisfying M &gt; 3.3 log (2N + 1). However, in the above, M is the number of bits of the code, and N is an integer not including "0". In the data multiplexing apparatus by code generation, a first differential part 2 which is differentiated in order to input an input video signal S1 to clarify the outline of an image, and an output of the first differential part 2 are input. A second derivative 4 for outputting a second differential signal in which a high frequency component is emphasized, a booster 6 for boosting a low level signal difference component by inputting an output of the second differential 4, and Input the output of the first differential part 92 to input an absolute value part 8 for taking an absolute value with a predetermined time difference and an output having a predetermined time difference between the absolute value part 8, and detect an edge after comparing with each other. Thereafter, the reshape unit 9 for outputting data, a delay unit 1 for delaying a predetermined time to compensate for the horizontal contour of the input image signal S1, and the output and reference generator of the booster unit 6 Compare the reference value of (10) to the predetermined bit The multiplication selector 30 for selecting and outputting the output data of the reshape unit 9 according to the output of the code generator 20 and the code generator 20, and the multiplication selector 30. And an adder (50) for outputting a horizontal contour-compensated image signal by adding an output and a delayed output of the delay unit (1).