KR0183935B1 - Adpcm compression/decompression apparatus and method - Google Patents

Abstract

An adaptive differential pulse code modulation type compression / decompression apparatus and method are disclosed. The apparatus includes means for storing an expected sample, calculating a final expected sample to examine the flow, or adding a second new sample and a final difference value, which have been previously output, and outputting it as a current second new sample; Decomposition selection signal SE and a step size SS and an output of the selection means in response to the compression / decomposition selection signal SE Means for performing an operation such as the size of the output * SS / 4) + SS / 8 and outputting the calculated result as a final difference value; means for adding the index value corresponding to the output of the selection means and the previous index value, Means for outputting a SS corresponding to a new index value, means for subtracting the expected sample from the first source sample to output a difference value, a first register for outputting SS in response to the SE, Compares the difference value with the SS output from the first register, subtracts a predetermined number of SSs from the difference value, subtracts a predetermined number of SSs from the subtracted value again to generate a first new sample, A second register for outputting the output of the selection means as a first new sample in response to the SE, and a second register for inverting the current second new sample input from the first means, And outputting the data in response to the SE, and is effective in terms of system operation and has the effect of reducing the size of the system.

Description

ADPCM compression / decomposition apparatus and method

The present invention relates to adaptive differential pulse code modulation (ADPCM) compression and decompression (ADPCM) techniques disclosed by the Digital Audio Technical Working Group (DATWG) under the Interactive Multimedia Association (IMA) more particularly, to an ADPCM compression / decompression apparatus and method capable of simultaneously performing ADPCM compression and decomposition.

FIG. 1 is a block diagram of a conventional ADPCM compression apparatus, and FIG. 2 is a block diagram of a conventional ADPCM decomposition apparatus.

The configuration and operation of the ADPCM compression and decompression apparatus shown in Figs. 1 and 2 are respectively disclosed in Patent Application Nos. 95-21013 and 95-30790, so that detailed description thereof will be omitted here.

As can be seen from the proposed patents, the ADPCM compression apparatus proposes a quantization adaptation method using a look-up table (LUT), and only detects differences between successive input linear data samples, The ADPCM decomposition apparatus detects the difference between the successive ADPCM data samples by using the correlation between the ADPCM data samples, encodes the difference value, And restores the value to a value close to the linear data before compression.

Meanwhile, in comparison with the conventional functions of the prior art, there is a problem that the size of the system is increased and the manufacturing cost of the system is increased because the respective functions are performed by separate hardware, despite the redundant functions.

SUMMARY OF THE INVENTION The present invention is directed to an ADPCM compression / decompression apparatus capable of continuously and repeatedly performing ADPCM compression and / or decomposition operations using a time division method.

According to another aspect of the present invention, there is provided a compression / decompression method performed in the ADPCM compression / decompression apparatus.

1 is a block diagram of a conventional ADPCM compression apparatus.

2 is a block diagram of a conventional ADPCM decomposition apparatus.

3 is a block diagram of an ADPCM compression / decompression apparatus according to the present invention.

4 shows an example of the configuration of the index table in the index decoder shown in Fig.

5 shows a configuration example of the step size table in the step size ROM shown in Fig.

In order to achieve the above object, there is provided an adaptive differential pulse code modulation (hereinafter referred to as ADPCM) code (hereinafter, referred to as a first (Hereinafter, referred to as " 2 " samples) of the 2N-bit complementary data (hereinafter referred to as " second complementary samples ") and / or an N-bit ADPCM code The pulse code modulation type compression / decompression apparatus stores a predicted sample and calculates a final expected sample to check the flow in the compressed mode, or in the decomposition mode, adds the final difference value to the second new sample that has been previously output Selecting means for inputting the second raw sample and the first new sample and selectively outputting one of the input values in response to a compression / decomposition selection signal; , And second means for size and performs operations as below by the output of the selecting means and outputs the operation result as the final difference value,

(The size of the selection means output * the step size / 4) + the step size / 8

A third means for obtaining a new index value by adding an index value corresponding to an output of the selection means and a previous index value and outputting the step size corresponding to the new index value, A first register for outputting the step size inputted from the third means in response to the compression / decomposition selection signal, The step size is compared with the step size output from the first register, the step size obtained by dividing the step size by a predetermined number is subtracted from the difference value, and the step size obtained by dividing the step size again by the predetermined number is subtracted from the subtracted value Fifth means for generating the first new sample and outputting the generated first new sample to the selecting means, Decomposition selection signal and outputting the output of the selection means as the first new sample in response to the compression / decomposition selection signal, and a second register for outputting the current second new sample inputted from the first means to the inverted compression / And a third register for outputting in response to the signal.

(Hereinafter, referred to as an " 1 ") code (hereinafter referred to as " 1 " (Hereinafter referred to as " second sample ") of the decomposed 2N-bit digital data (hereinafter referred to as " second new sample ") or outputting an N-bit ADPCM code The differential pulse code modulation method compression / decompression method includes the steps of: determining whether the compression mode is the decompression mode; converting the first raw sample to the first new sample when the compression mode is the compression mode; , And decomposing the second raw sample into the second new sample.

Hereinafter, the configuration and operation of the ADPCM compression / decompression apparatus according to the present invention will be described with reference to the accompanying drawings.

Prior to describing the present invention, the present invention performs a compression or decomposition operation based on a reference algorithm disclosed in IMA.

3 is a block diagram of an ADPCM compression / decompression apparatus according to the present invention. The first block 10, the selection unit 72, the second block 20, the third block 30, A first register 64 and a logical product 62, a fifth block 50, a second register 74 and a logical product 76, a third register 102, (100).

The first block 10 shown in FIG. 3 stores the predicted sample and calculates the final expected sample to check the flow in the compressed mode, or, in the decomposition mode, adds the last difference value to the second new sample, And outputs the result as a current second new sample OUT2. In the compressed mode, the final difference value and the previous expected sample are added and output as the final estimated sample. In the decomposed mode, the final difference value and the previous A first adder 14 for adding and outputting a second new sample, and for checking the overflow of the final estimated sample output from the first adder 14 in the compressed mode and storing the expected sample, And a first register and a limiter 12 for checking and outputting an overflow of a second new sample output from the adder 14.

The selection unit 72 performs a function of inputting the second raw sample IN2 and the first new sample OUT1 and selectively outputting one of the input values in response to the compression / decomposition selection signal SE It is implemented as a multiplexer.

The second block 20 receives the step size and the output of the selection unit 72 and performs an operation such as the following Equation 1 and outputs the calculated result as a final difference value, A switching unit 26 for selectively outputting the step size inputted from the register 28 in response to the output of the selecting unit 72; Which outputs the output of the second adder 24 and the second adder 24 and the output of the selector 72 as the final difference value by performing the exclusive-OR operation on the most significant bit among the outputs of the first adder 24 and the output of the register 28, And a logical sum 22.

[Size of output of selection unit 72 * Step size / 4] + Step size / 8

The third block 30 performs a function of obtaining a new index value by adding an index value corresponding to an output of the selection unit 72 and a previous index value and outputting a step size corresponding to a new index value, An index decoder 38 for decoding the output of the selector 72 and outputting an index value corresponding to the decoded value, a third adder 38 for adding the index value output from the index decoder 38 to the previous index value, A second register for checking the flow of the output of the third adder 36 and a step size corresponding to the output of the limiter 34 and the second register and limiter 34 to the first register 64, And a step size ROM table 32 for outputting the result to the register 28 of the second block 20.

The fourth block 40 performs the function of subtracting the expected sample from the first source sample IN1 in the compressed mode and outputting the difference value. The first block of the first block 10 and the limiter 12 A first storage unit 42 for outputting the inputted first source sample IN1 in response to the compression / decomposition selection signal SE, a first inverter 44 for inverting the output of the first inverter 44, (44) and the output of the first storage unit (42), and a fourth adder (46) and a fourth adder (46) for performing an exclusive OR operation on the sign bit and the data bit among the outputs of the fourth adder And a 2-bit exclusive logical OR (48).

The first register 64 and the logical product 62 perform the function of outputting the step size inputted from the step size ROM table 32 of the third block 30 in response to the compression / decomposition selection signal SE .

The fifth block 50 compares the difference value with the step size output from the first register 64 in the compression mode, subtracts the step size obtained by dividing the difference by a predetermined number from the difference value, divides the step size by a predetermined number A second storage unit 52 for temporarily subtracting the difference value from the subtracted value to generate a first new sample and outputting the generated first new sample to the selection unit 72, A first multiplexer 58 for selectively outputting the step size output from the first register 64 in response to the control clock CKL2 and a second inverter 58 for inverting the output of the first multiplexer 58 A second multiplexer 54 for selectively outputting the output of the second storage unit 52 and the first addition value in response to the sign bit of the first addition value, And the output of the second inverter 82 to output as a first added value A third storage unit 88 for temporarily storing the first addition value and outputting the first addition value to the second multiplexer 54, a third inverter 86 for inverting and outputting the first addition value, A third multiplexer 56 and a third multiplexer 56 for inputting the output of the fourth adder 46 and the output of the third inverter 86 and selectively outputting the input value in response to the control clock CKL2, And a fourth storage unit 90 for temporarily storing the output of the first sample as a first new sample.

The second register 74 and the logical product 76 perform the function of outputting the output of the selection unit 72 as a first new sample OUT1 in response to the compression / decomposition selection signal SE.

The third register 102 and the AND gate 100 add the current second new sample input from the first register of the first block 10 and the limiter 12 to the inverted compression / ) In response to the command.

FIG. 4 shows an example of the structure of the index table in the index decoder 38 shown in FIG.

5 shows a configuration example of the step size table in the step size ROM 32 shown in FIG.

Hereinafter, in order to facilitate understanding of the ADPCM compression / decompression apparatus according to the present invention, ADPCM compression will be separately described as follows.

The data input to the ADPCM compression unit is a 16-bit binary complement and is called a primitive sample. A 4-bit ADPCM sample output through compression is defined as a new sample. In the compression process, the difference between the raw sample and the expected sample (estimate sample) is calculated, and the difference value is quantized into a 4-bit new sample using the step size to obtain the compressed data. The compressed data has a data format indicating a 4-bit new sample, in which the MSB bit indicates a sign and the remaining bits indicate a size. After the output of the new sample value, this value is again calculated as a linear difference value through the decomposer using the same quantization step size, and the calculated difference value is multiplied by 1/2 to compensate for the truncation error due to quantization. Is added. The final difference value thus added to the difference value to the correction value is added back to the previous expected sample and subtracted the final expected sample from the input raw sample.

The new sample specifies the index of the step size table, and the specified index specifies the new step size of the step size table. Here, the expected sample, step size, and index should have a static variable between the sample and the sample.

Then, for example, let's explain the compression process as follows. If the raw sample is 873F (hex), the expected sample is 8700 (hex), the step size is 73 (decimal) and the index is 24 (decimal), first subtract the expected sample from the raw sample to calculate the difference. At this time, if the difference value is 0 or more, the sign bit is 0, otherwise, the sign bit is 1. If the difference value is negative, the difference value is treated as a negative value. Second, divide the difference value by the step size. That is, if the difference value is equal to or larger than the step size, the ADPCM data [2] = 1. However, in the example, since the difference value is smaller than the step size, the ADPCM data [2] = 0 is obtained. When this calculation is completed, the step size is shifted one bit to the right by one bit (division 2), and subtracting the step size value (36 bits resulting from 1 bit shifting to the right) from the difference value. Since the result of subtraction is 27, ADPCM data [1] = 1 is obtained, and 18, which is a value obtained by shifting the step size to the right by one bit, is subtracted from 27. [ The subtracted result 9 indicates that the ADPCM data [0] = 1. As a result, the 4-bit ADPCM data [3: 0] = 0011 is obtained.

Using the obtained ADPCM data [3: 0], the final difference value is obtained using the following equation (2).

(3 bit size * step size / 4) + (step size / 8)

If the final difference value is found, then adding the final difference value to the previous expected sample, this value becomes the final expected sample to be subtracted from the next entered raw sample. At this time, the final difference value is added (sign bit = 0) or subtracted (sign bit = 1) by the sign bit of the 4-bit ADPCM data.

The final expected sample is subjected to an overflow check before it is computed with the raw sample. Also, by moving the index table shown in FIG. 3 using the generated ADPCM data (new sample), one new step size can be designated in the step size table of FIG. In this example, the new sample is 0011, and the value of the designated index is 24, indicating that the step size 73 of the 89 step size table values is the 24th value. Here, since the decimal value of the new sample is 3, a new index value is obtained by adding the third number -1 in the index table and the previous index 24. Therefore, the 23rd step number 66 in the step size table becomes a new step size. A new sample that determines the index table can be mapped to the index table from 0 to 15, considering only the size, ignoring the sign.

Next, the ADPCM decomposition will be described separately as follows.

The data input to the ADPCM decomposition apparatus is a 4-bit ADPCM code. This data is called a raw sample, and 16-bit complement data output through decomposition is called a new sample. In this process, the linear difference value is calculated using the correlation between the raw sample and the quantization step size (the value of the quantization LUT). During the calculation of this difference value, 1/2 is added to correct the truncation error of the quantization. By adding the calculated linear difference value to the new sample (the previous sample), a final linear new sample is obtained. This final output value, the new sample, is output from the entire system as disassembled data in 16-bit two's complement format. The raw sample adjusts the index in the step size table and the adjusted index specifies the new step size of the step size table. This newly specified step size value will produce the next input raw sample and linear difference value. Here, the new sample, step size, and index must have a positive variable between the sample and the sample. As in the compression process, the above-described decomposition process will be described as follows, for example.

If the raw sample is 0011, the new sample (previous sample) is 8700 (hex), the step size is 73 (decimal), and the index is 24 (decimal), first let the initial initial value be zero.

In the first decomposition process, a difference value as shown in the following Equation 3 is obtained using the relationship between the raw sample and the step size.

Difference value = (raw sample + 1/2) * step size / 4

= (Raw sample * step size / 4) + (step size / 8)

In Equation (3), the raw sample means a size of 3 bits. Therefore, by substituting the size 011 of 3 bits into the raw sample and substituting 73 for the step size, the difference value is 63 = 3F (hex). If the MSB of the original sample, that is, the sign bit is 1, the difference value is treated as a negative value.

In the second decomposition process, a linear new sample of the final 16-bit two's complement format is obtained by adding the new sample value to the difference value obtained in the first procedure. The values thus obtained are checked for overflow and underflow.

That is, a new sample is determined by the first and second steps, and the input raw sample determines the new step size to be computed with the next input raw sample. The index table of FIG. 4 is moved by using the raw sample, and one value of the step size table of FIG. 5 is designated. That is, the index is defined by the following equation (4).

Index = value in the index table at the position corresponding to the previous index + raw sample value

Here, since the value located in the index table at the position corresponding to the raw sample value 3 (011) is -1, the value 23 obtained by subtracting 1 from the previous index 24 becomes the new index, and the step size table The value 66 on the new step size becomes the new step size. A primitive sample that determines an index table is mapped to an index table of 0 to 15 considering only the size, ignoring the sign.

Meanwhile, the apparatus according to the present invention shown in FIG. 3 uses a clock mainly used in a digital audio apparatus as a master clock.

The apparatus according to the present invention shown in Fig. 3 stores a first raw sample in a 16-bit two's complement format through an input terminal IN1 and stores it in a register 42. The stored sample is supplied to a fourth adder 46 . At this time, the register 42 is controlled by the output of the logical product 62. Here, the logical product 62 is operated by the two input compression / decompression selection signals SE and the latch clock CLK1, where SE is high in the compressed mode and SE is low in the decomposition mode. Another input of the fourth adder 46 is input through the first inverter 44 via the first register and limiter 12 as a final estimated sample. Here, the first inverter 44 serves to invert the entire data before the input of the fourth adder 46 to subtract the expected samples from the raw samples. The input data (the first source sample) and the final estimated sample are computed in the fourth adder 46, and the result is the difference value. If the difference value is 0 or more, the sign bit is 0. If the difference value is negative, the sign bit is 1. If the sign bit is 1, the difference value should be treated as a negative number. This operation is performed by the second exclusive logical OR 48 and the sign bit is also stored in the register 90 through the third multiplexer 56. [

The data that has passed through the second exclusive OR 48 is stored in the second storage 52 and this data is input to the fifth adder 84 via the second multiplexer 54 as one input. On the other hand, the step size value is input to the first register 64 from the step size table stored in the step size table ROM 32, and the first register 64 is controlled by the output of the logical product 62, do. The output data of the first register 64 is inverted through the second inverter 82 via the selected data path through the first multiplexer 58 and enters the input of another one of the fifth adders 84. The two data input to the fifth adder 84 are immediately subjected to the difference value and the step size value as the difference value + step size in the fifth adder 84. In the added result, the MSB sign bit is inverted through the third inverter 86, and the inverted data is stored in the shift register 90 through the third multiplexer 56. The MSB sign bit is first stored in the shift register 90 through the third multiplexer 56, and the MSB sign bit is first stored in the shift register 90, The result of the operation is also stored in the shift register 90 through the third multiplexer 56 to determine the value of the ADPCM data [2]. The step size is input to the first multiplexer 58 through the ROM 32 and the first register 64 without changing the step size. At this time, the step size is shifted by one bit to obtain the effect of the division 2. The data shifted by one bit to the right is input to the fifth adder 84 via the second inverter 82 and the result previously calculated through the fifth adder 84 is stored in the third storage 88 , And if the MSB bit is 0, it is input to the fifth adder 84 via the second multiplexer 54 and is shifted to the right by 1 bit to the right of the second step size . As a result of this operation, the MSB sign bit is inverted through the third inverter 86 and the inverted data is also stored in the shift register 90 via the third multiplexer 56. [ In this case, when the MSB bit of the data stored in the third storage unit 88 is 1, the data of the second storage unit 52 is input to the fifth adder 84 through the second multiplexer 54, . Thus, the second data stored in the shift register 90 becomes the ADPCM data [1]. When the ADPCM data [0] is stored in the shift register 90, the ADPCM data [3: 0] is simultaneously output as parallel data, and the second register 74 ). And finally outputted through the output terminal OUT1 in the form of ADPCM 4-bit data (first new sample). Here, the selector 72 outputs the result of the shift register 90 in the compressed mode, and outputs the second raw sample input through the input terminal IN2 in the decomposition mode. To this end, the second register 74 is under the control of the logical product 76, and the ADPCM data (the first new sample) is finally added to the second register 74 only if SE of the two inputs of the logical product 76 is high .

The step size value output from the ROM 32 is outputted to and stored in the register 28 and the step size value stored in the register 28 is outputted to the second adder 24 having the switch 26 and the four inputs do. Each of the data bits of the 3-bit data [2: 0] excluding the MSB code bits of the 4-bit parallel data output from the selector 72 controls the three switches of the switch 26 for each bit. The output data of the first switch is input to the second adder 24 without shifting, the output of the second switch is shifted by one bit to the right, and the third output is shifted to the right by two bits to be input to the second adder 24. Another output of the register 28 is shifted 3 bits to the right and enters the input of the other one of the second adders 24. The result of the calculation of the four input data in the second adder 24 is controlled by the first exclusive OR (22). The control value of the first exclusive OR circuit 22 is the sign bit of the 4-bit ADPCM data output from the selector 72. Until now, the operation of obtaining the final difference value from the ADPCM data [3: 0], that is, the operation of the equation (2) has been described.

On the other hand, the output of the first exclusive OR gate 22 is again input to the first adder 14, which is the final difference value, and the data output from the first register and the limiter 12 is the previous expected sample value . The two input data are added in the first adder 14 and stored in the first register and the limiter 12 again. The result of the operation of the first adder 14 becomes the final expected sample to be subtracted from the next input raw sample and the overflow is checked before this result is stored in the first register and limiter 12 . The role of checking this overflow is done by the limiter. That is, if the expected sample is greater than 32767, the expected sample is 32767, but if the expected sample is less than -32768, the expected sample is -32768.

Finally, the third block 30 for mapping the index table using 4-bit ADPCM data, which is the output data of the selector 72, will be described.

The index decoder 38 receives the generated ADPCM data and processes it as an absolute value, and designates one of the 16 values of the index table shown in FIG. 4 as the processed absolute value. Data is output according to the designated value, and the output value is input to the third adder 36. [ At this time, the index value previously designated from the second register and limiter 34 is input to the third adder 34 so that both data are calculated and the result is stored again in the second register and limiter 34, A new step size table value on the ROM 32 is designated as an index value. As a result, the ROM 32 outputs a new step size value. The new index value is input to the second register and limiter 34 to check the index overflow and the underflow. That is, if the index is less than 0, the index is 0. If the index is greater than 88, the index is 88. This operation is performed by a limiter.

Hereinafter, the decomposition process performed in the compression / decompression apparatus according to the present invention shown in FIG. 3 will be described as follows.

The device shown in FIG. 3 inputs a second raw sample through an input terminal IN2, and the input data is input in a 4-bit ADPCM format. The input data is output to the index decoder 38, the switch 26 and the first exclusive OR circuit 22 via the selector 72. [

The ROM 32 stores the step size value and outputs the value to the first register 64 and the register 28, respectively. The first register 64 can not accept data when the apparatus is performing a disassembly operation, and only the register 28 accepts data output from the ROM 32. The register 28 stores the step size table value and outputs the value to the switch 26 and the third adder 24. When the register 26 outputs data, the switch 26 receives the data and receives 3 bits excluding the MSB (sign bit) bits of the 4-bit ADPCM data output from the selector 72 as a control clock Each of the switch stages is controlled. The switch 26 receives the first, second, and third switches in sequence from the MSB next bit of the 4-bit ADPCM data. When the value of each bit is 1, the switch passes the data. When the bit is 0, . The first switch stage passes the data as it is, the second switch stage passes the data shifted to the right by one bit, the third switch stage passes the data shifted to the right by two bits, and the third adder 24, . The other output line of the register 28 is shifted to the right by 3 bits, and this line is output to the second adder 24 without the control of the switch. The second adder 24 inputs the output of the switch 26 and the output data of the register 28 to perform an addition operation and outputs the result to the first exclusive OR 22. The first exclusive OR operator 22 receives the MSB sign bit among the results output from the selector 72 and receives the output of the second adder 24. If the MSB sign bit is 0, And if it is 1, it performs the function of inverting and outputting the data. That is, the register 28, the switch 26, the second adder 24, the first exclusive OR circuit 22, and the selector 72 perform the functions of Equation (1).

The output of the first exclusive OR circuit 22 corresponds to a difference value which is again input to the first adder 14 and added to the output data of the first register and the limiter 12, And outputted through the first register and the limiter 12. [ The output is data having a 16-bit 2's complement format, and is output data resulting from decomposing 4-bit ADPCM data. At this time, the third register 102 latches the output result of the first register and the limiter 12 under the control of the logical product 100, and the third register 102 latches the result of the second new sample Through the output terminal OUT2. The output of the logical product (100) is normally output when SE is zero. That is, the third register 102 operates only in the decomposition mode. The output of the first register and limiter 12 acts as the previous sample and is then operated on with the difference value input to the first adder 14. That is, the functions of the first adder 14, the first register and the limiter 12, the register 102, and the logical product 100 are as follows: a second new sample is obtained and a function of checking overflow and underflow .

Second new sample = previous second new sample + difference value

The 4-bit ADPCM data of the selector 72 is input to the index decoder 38. One of the 16 index table values is selected by the absolute value of the input value, and the selected value is input to the third adder 36 . The values output from the second register and the limiter 34 are fed back to the third adder 36 and the new index value and the third adder 36 are operated to output the result. The output of the third adder 36 is input to and stored in the second register and the limiter 34. When added to a new index value that is input next to the previous index value, The limiter function for checking whether the size of the table is larger or smaller than the range of 0 to 88 is also processed by the second register and limiter 34 and the final result is output to the ROM 32 storing the step size table value . The ROM 32 to which the value is input outputs one selected data out of the 89 step size table values to the register 28 and the output data of the ROM 32 serves as the value of the new step size. That is, the functions of the selector 72, the index decoder 38, the third adder 36, the second register, the limiter 34, and the ROM 32 function to obtain the following indexes.

Index = value of position on index table corresponding to previous index + second raw sample value

The above-mentioned ADPCM system is based on the algorithm disclosed in DATWG, and mainly uses four main sampling rates of 8.0KHz, 11.025KHz, 22.05KHz, and 44.1KHz. As the fastest sampling rate, it is mainly used for digital audio equipment that uses 44.1KHz. By using the master clock used in general digital audio equipment (mainly using 16.9344MHz) and using the time division method appropriately, It is realized by one hardware.

INDUSTRIAL APPLICABILITY As described above, the ADPCM compression / decompression apparatus and method according to the present invention realize the ADPCM compression / decompression function using a single hardware by using a time division method, .

Claims (7)

2-bit complement data (hereinafter referred to as first raw sample) of 2N bits is input and compressed, (ADPCM) code (hereinafter referred to as a first new sample) and / or an N-bit ADPCM code (second source sample) (Hereinafter, referred to as " second new sample "), comprising: In a compressed mode, a predicted sample is stored and a final estimated sample is calculated to check the flow, or in a decomposition mode, the second new sample and the final difference value, which have been previously output, are added and output as a current second new sample 1 means; Selection means for inputting the second raw sample and the first new sample and selectively outputting one of the input values in response to a compression / decomposition selection signal; Second means for inputting a step size and an output of the selection means to perform the following operation and outputting the calculated result as the final difference value; (The size of the selection means output * the step size / 4) + the step size / 8 Third means for obtaining a new index value by adding an index value corresponding to an output of the selecting means and a previous index value and outputting the step size corresponding to the new index value; A fourth means for, in the compressed mode, subtracting the expected sample from the first raw sample to output a difference value; A first register for outputting the step size inputted from the third means in response to the compression / decomposition selection signal; Wherein the step size is obtained by comparing the difference value with the step size output from the first register and subtracting the step size obtained by dividing the difference by a predetermined number from the difference value, Fifth means for generating the first new sample and outputting the generated first new sample to the selection means; A second register for outputting the output of the selection means as the first new sample in response to the compression / decomposition selection signal; And And a third register for outputting the current second new sample inputted from the first means in response to the inverted compression / decomposition selection signal. 2. The apparatus of claim 1, wherein the first means In a decompression mode, adding the final difference value and the previous expected sample to output as the final estimated sample, and in a decomposition mode, adding the final difference value and the previous second new sample and outputting, ; And In the compression mode, the overflow of the final estimated sample output from the first addition means is checked and the expected sample is stored. In the decomposition mode, the overflow of the second new sample output from the first addition means And a limiter for comparing the first register and the second register. 3. The apparatus according to claim 1 or 2, wherein the second means A register for inputting the step size and shifting a predetermined number of times and outputting the result; Switching means for selectively outputting the step size inputted from the register in response to an output of the selecting means; Second adding means for adding the output of the switching means and the output of the register; And And a first exclusive logical OR for exclusive-ORing the output of the second addition means and the most significant bit among the outputs of the selection means and outputting the result as the final difference value. 4. The apparatus of claim 3, wherein the third means An index decoder for decoding the output of the selecting means and outputting the index value corresponding to the decoded value; Third adding means for adding the index value output from the index decoder to the previous index value; A second register and a limiter for checking the flow of the third addition means output; And And a ROM table for outputting the step size corresponding to the output of the second register and the limiter to the first register and the second means. 5. The apparatus according to claim 4, wherein said fourth means A first inverter for inverting and outputting an output of the first means; First storing means for outputting the input first raw sample in response to the compression / decomposition selection signal; Fourth adding means for adding the output of the first inverter and the output of the first storing means and outputting the result; And And a second exclusive-OR circuit for exclusive-ORing the sign bit and the data bit in the output of the fourth addition means and outputting the result as the difference value. 6. The apparatus of claim 5, wherein the fifth means Second storing means for temporarily storing the difference value; A first multiplexer for selectively outputting the step size output from the first register in response to a control clock; A second inverter for inverting and outputting the output of the first multiplexer; A second multiplexer for selectively outputting an output of the second storage means and a first addition value in response to a sign bit of the first addition value; Fifth adding means for adding the output of the second multiplexer and the output of the second inverter and outputting the result as the first addition value; Third storing means for temporarily storing the first addition value and outputting the first addition value to the second multiplexer; A third inverter for inverting and outputting the first addition value; A third multiplexer for inputting the output of the fourth addition means and the output of the third inverter and selectively outputting the input value in response to the control clock; And And a fourth storing means for temporarily storing the output of the third multiplexer and outputting the output as the first new sample. 2-bit complement data (hereinafter referred to as first raw sample) of 2N bits is input and compressed, (ADPCM) code (hereinafter referred to as a first new sample) and / or an N-bit ADPCM code (second source sample) (Hereinafter, referred to as " second new sample "), the method comprising the steps of: Determining whether compression mode or decomposition mode is selected; Converting the first raw sample to the first new sample when in the compressed mode; And And decomposing the second original sample into the second new sample when the decomposition mode is the decomposition mode.