KR970004324A - Variable delay - Google Patents
Variable delay Download PDFInfo
- Publication number
- KR970004324A KR970004324A KR1019950018858A KR19950018858A KR970004324A KR 970004324 A KR970004324 A KR 970004324A KR 1019950018858 A KR1019950018858 A KR 1019950018858A KR 19950018858 A KR19950018858 A KR 19950018858A KR 970004324 A KR970004324 A KR 970004324A
- Authority
- KR
- South Korea
- Prior art keywords
- delay
- line
- variable
- buffer elements
- inputting
- Prior art date
Links
Abstract
가변형 지연기는 지연량을 조절하여 구동전압 및 주위의 온도의 변화에 따라 지연시간의 오차를 보상한다. 이를 위하여, 상기 가변형 지연기는 지연대상신호를 입력하기 위한 입력라인과, 지연조절신호를 입력하기 위한 제어라인과, 상기 입력라인 및 출력라인의 사이에 직렬 접속된 적어도 2개 이상의 완충소자와, 상기 적어도 2개 이상의 완충소자들간의 적어도 하나 이상의 접속점에 접속된 적어도 1개 이상의 캐패시터와, 상기 제어라인으로부터의 상기 지연조절신호에 의하여 상기 적어도 1개 이상의 캐패시터의 충방전 시간을 조절하도록 설치된 적어도 1개 이상의 MOS 트랜지스터를 구비한다.The variable retarder adjusts the amount of delay to compensate for the error of delay time according to the change of driving voltage and ambient temperature. To this end, the variable delay device includes an input line for inputting a delay target signal, a control line for inputting a delay control signal, at least two buffer elements connected in series between the input line and the output line, At least one capacitor connected to at least one connection point between at least two buffer elements and at least one arranged to adjust the charge and discharge time of the at least one capacitor by the delay control signal from the control line The above MOS transistor is provided.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 종래의 지연기의 회로도.1 is a circuit diagram of a conventional retarder.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018858A KR970004324A (en) | 1995-06-30 | 1995-06-30 | Variable delay |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018858A KR970004324A (en) | 1995-06-30 | 1995-06-30 | Variable delay |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970004324A true KR970004324A (en) | 1997-01-29 |
Family
ID=66526606
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950018858A KR970004324A (en) | 1995-06-30 | 1995-06-30 | Variable delay |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970004324A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100380593B1 (en) * | 2000-06-15 | 2003-04-18 | 보은군 | Method for forming a loessball |
KR100489587B1 (en) * | 1997-12-29 | 2005-08-23 | 주식회사 하이닉스반도체 | Time delay circuit |
-
1995
- 1995-06-30 KR KR1019950018858A patent/KR970004324A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100489587B1 (en) * | 1997-12-29 | 2005-08-23 | 주식회사 하이닉스반도체 | Time delay circuit |
KR100380593B1 (en) * | 2000-06-15 | 2003-04-18 | 보은군 | Method for forming a loessball |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |