KR970004100A - Integrated Circuits with Linear Thin Film Capacitors - Google Patents

Integrated Circuits with Linear Thin Film Capacitors Download PDF

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KR970004100A
KR970004100A KR1019960019906A KR19960019906A KR970004100A KR 970004100 A KR970004100 A KR 970004100A KR 1019960019906 A KR1019960019906 A KR 1019960019906A KR 19960019906 A KR19960019906 A KR 19960019906A KR 970004100 A KR970004100 A KR 970004100A
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integrated circuit
dielectric region
electrode
forming
capacitor
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KR1019960019906A
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Korean (ko)
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마일즈 오브리안 2세 헨리
켄트 와츠 로데릭
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로버트 이. 루드닉
에이 티 앤드 티 아이피엠 코포레이션
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Publication of KR970004100A publication Critical patent/KR970004100A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

능동 디바이스를 갖는 집적회로는 X, Y, Z의 값이 각각 대략 2, 9, 20의 비율이 되는 BaxTiyOz의 박막 유전영역을 사용하는 커패시터에 전기적으로 접속되어 있다. 상기 집적회로의 커패시터는 작은 치수, 낮은 유출 플럭스(flux)를 가지고 광범위한 주파수와 바이어스 전압에 걸처 거의 선형인 커패시턴스를 갖는다.An integrated circuit having an active device is electrically connected to a capacitor using a thin film dielectric region of Ba x Ti y O z where the values of X, Y, and Z are approximately 2, 9, and 20, respectively. Capacitors in such integrated circuits have small dimensions, low outflow flux and nearly linear capacitance over a wide range of frequencies and bias voltages.

Description

선형 박막 커패시터를 가진 집적회로Integrated Circuits with Linear Thin Film Capacitors

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 집적회로의 능동 디바이스와 선형 박막 커패시터를 도시하는 단면도.1 is a cross-sectional view showing an active device and a linear thin film capacitor of an integrated circuit according to the present invention.

Claims (21)

집적 회로에 있어서, 상기 능동 디바이스에 전기적으로 연결된 커패시터를 포함하며, 상기 커패시터는 제1 및 제2전기적 도전성 전극 사이에 삽입된 유전영역을 가지며, 상기 유전영역은 X, Y, Z의 값이 각각 대략2, 9, 20의 비율이 되는 대체로 다결정 구조를 가진 BaxTiyOz의박막을 포함하는 것을 특징으로 하는 집적회로.An integrated circuit comprising: a capacitor electrically connected to the active device, the capacitor having a dielectric region interposed between the first and second electrically conductive electrodes, the dielectric region having values of X, Y, and Z, respectively. An integrated circuit comprising a Ba x Ti y O z thin film having a generally polycrystalline structure at a ratio of approximately 2, 9, 20. 제1항에 있어서, 상기 영역은 10%와 20%의 범위의 Ba몰 퍼센티지와 90% 내지 80%의 대응하는 범위에서의 Ti몰 퍼센티지를 포함하는 것을 특징으로 하는 집적회로.The integrated circuit of claim 1, wherein the region comprises a Ba mole percentage in the range of 10% and 20% and a Ti mole percentage in the corresponding range of 90% to 80%. 제1항에 있어서, 상기 유전영역은 제1 및 제2전극사이에서 대략 50 내지 150nm 범위의 두께를 갖는 것을 특징으로 하는 집적회로.The integrated circuit of claim 1 wherein the dielectric region has a thickness in the range of approximately 50 to 150 nm between the first and second electrodes. 제3항에 있어서, 상기 유전영역의 두께가 100nm 보다 큰 것을 특징으로 하는 집적회로.4. The integrated circuit of claim 3 wherein the thickness of the dielectric region is greater than 100 nm. 제1항에 있어서, 상기 제1전극이 반도체칩의 절연층 위에서 형성되는 것을 특징으로 하는 집적회로.The integrated circuit of claim 1, wherein the first electrode is formed on an insulating layer of a semiconductor chip. 제1항에 있어서, 상기 제1전극이 상기 집적회로의 반도체 기판의 물질과 상기 유전막 사이의 화확반응을 대체적으로 방지하는 장벽이 되는 것을 특징으로 하는 집적회로.2. The integrated circuit of claim 1 wherein the first electrode serves as a barrier to substantially prevent chemical reaction between the material of the semiconductor substrate of the integrated circuit and the dielectric film. 제6항에 있어서, 상기 제1전극이 폴라티늄 하부에 탄탈륨이 있는 2층 구조인 것을 특징으로 하는 집적회로.7. The integrated circuit of claim 6, wherein the first electrode is a two-layer structure having tantalum under the platinum. 제1항에 있어서, 상기 커패시터가 금속-절연체-금속 구성을 갖는 것을 특징으로 하는 집적회로.2. The integrated circuit of claim 1 wherein the capacitor has a metal-insulator-metal configuration. 제1항에 있어서, 상기 커패시터가 평행판 구조를 갖는 것을 특징으로 하는 집적회로.The integrated circuit of claim 1, wherein the capacitor has a parallel plate structure. 반도체 기판상에 집적회로 커패시터를 형성하는 방법에 있어서, 제1전극을 형성하는 단계와, X, Y, Z의 값이 각각 대략 2, 9, 20의 비율이 되는 상기 제1전극상의 BaxTiyOz의 박막을 포함하는 유전영역을 형성하는 단계와, 상기 제1전극 맞은편의 유전막층 상에 제2전극을 형성하는 단계를 포함하는 것을 특징으로 하는 집적회로 커패시터 형성방법.A method of forming an integrated circuit capacitor on a semiconductor substrate, the method comprising: forming a first electrode and Ba x Ti on the first electrode such that the values of X, Y, and Z are approximately 2, 9, and 20, respectively; and forming a dielectric region including a thin film of y O z , and forming a second electrode on the dielectric layer layer opposite the first electrode. 제10항에 있어서, 상기 유전영역을 형성하는 단계는 BaxTiyOz타겟을 이용하여 무선 주파수 마그네트론에 의해 상기 막을 디포지션하는 단계를 더 포함하는 것을 특징으로 하는 집적회로 커패시터 형성 방법.The method of claim 10, wherein forming the dielectric region further comprises depositing the film by a radio frequency magnetron using a Ba x Ti y O z target. 제10항에 있어서, 상기 제1전극이 집적회로의 영역 상에 형성되고, BaxTiyOz의 박막이 디포지트되는 동안에 상기 제1전극을 갖는 상기 집적회로를 400℃ 내지 650℃의 온도범위에 두는 단계를 더 포함하는 것을 특징으로 하는 집적회로 커패시터 형성방법.The integrated circuit of claim 10, wherein the integrated circuit having the first electrode is formed at a temperature of 400 ° C. to 650 ° C. while the first electrode is formed on an area of an integrated circuit and a thin film of Ba x Ti y O z is deposited. An integrated circuit capacitor forming method comprising the step of placing in the range. 제12항에 있어서, 상기 집적회로를 가열하는 상기 단계가 3 내지 10분동안에 상기 온도에 놓여지고, 수시간 동안의 디포지션 후 가열된 집적회로가 냉각되도록 하는 단계를 더 포함하는 것을 특징으로 하는 집적회로 커패시터 형성방법.13. The method of claim 12, wherein the step of heating the integrated circuit further comprises the step of placing at the temperature for 3 to 10 minutes and allowing the heated integrated circuit to cool after several hours of deposition. Integrated circuit capacitor formation method. 제10항에 있어서, Ar과 O2의 환경에서 상기 유전영역을 형성하는 단계를 더포함하는 것을 특징으로 하는 집적회로 커패시터 형성방법.11. The method of claim 10, further comprising forming the dielectric region in an environment of Ar and O 2 . 제14항에 있어서, 상기 유전영역을 형성하는 상기 단계는 대략 30 내지 50mTorr의 압력에서 상기 Ar/O2환경을 유지하는 단계를 더 포함하는 것을 특징으로 하는 집적회로 커패시터 형성방법.15. The method of claim 14 wherein the step of forming the dielectric region further comprises maintaining the Ar / O 2 environment at a pressure of approximately 30-50 mTorr. 제10항에 있어서, 다결정구조가 상기 유전영역을 어닐링하는 단계에 의해서 이루어지는 것을 특징으로하는 집적회로 커패시터 형성방법.11. The method of claim 10 wherein the polycrystalline structure is formed by annealing the dielectric region. 제10항에 있어서, 상기 제1전극이 상기 집적회로의 영역상에 형성되고, 상기 집적회로의 물질과 상기 유전영역 사이에서 화학반응을 실질적으로 방지하는 장벽을 또한 제공하는 것을 특징으로 하는 집적회로 커패시터 형성방법.12. The integrated circuit of claim 10, wherein the first electrode is formed on an area of the integrated circuit and also provides a barrier that substantially prevents chemical reaction between material of the integrated circuit and the dielectric region. How to form a capacitor. 제17항에 있어서, 상기 제1전극을 형성하는 상기 단계가 플라티늄과 탄탈륨의 2층 구조를 형성하는 단계를 더 포함하고, 상기 탄탈륨은 상기 집적회로의 상기 영역과 접속하여 형성되고 상기 플라티늄은 상기 유전영역과 접촉하는 것을 특징으로 하는 집적회로 커패시터 형성방법.18. The method of claim 17, wherein the forming of the first electrode further comprises forming a two-layer structure of platinum and tantalum, wherein the tantalum is formed in contact with the region of the integrated circuit and the platinum is An integrated circuit capacitor forming method comprising contacting a dielectric region. 제1항에 있어서, 상기 유전영역이 대체로 아몰퍼스의 구조를 포함하는 것을 특징으로 하는 집적회로.2. The integrated circuit of claim 1 wherein the dielectric region comprises a structure of an amorphous structure. 제10항에 있어서, 상기 형성된 유전영역이 대체로 아몰퍼스 구조를 포함하는 것을 특징으로 하는 집적회로 커패시터 형성방법.12. The method of claim 10 wherein the formed dielectric region comprises a substantially amorphous structure. 제10항에 있어서, 상기 형성된 유전영역이 10% 내지 20% 범위의 Ba몰 퍼센티지와 90% 내지 80% 범위의 대응하는 Ti몰 퍼센티지를 포함하는 것을 특징으로 하는 집적회로 커패시터 형성방법.12. The method of claim 10 wherein the dielectric region formed comprises a Ba mole percentage in the range of 10% to 20% and a corresponding Ti mole percentage in the range of 90% to 80%. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960019906A 1995-06-07 1996-06-05 Integrated Circuits with Linear Thin Film Capacitors KR970004100A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US617,976 1975-09-29
US47405095A 1995-06-07 1995-06-07
US474,050 1995-06-07
US61797696A 1996-03-15 1996-03-15

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TW319915B (en) 1997-11-11

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