JPH09116093A - Integrated circuit with linear thin-film capacitance - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit having linear thin-film capacitance. SOLUTION: This integrated circuit 1 has an active device 10 electrically connected to capacitance 5 using the thin-film dielectric region 75 of BaxTiyOz, and the values of x, y and z are represented by the ratio of 2, 9 and 20. The capacitance of such an integrated circuit 1 has approximately linear capacitance in compact size, low leakage electric flux, wide frequency and a bias voltage range.

Description

Detailed Description of the Invention

FIELD OF THE INVENTION The present invention relates generally to integrated circuits, and more specifically to integrated circuits using compact thin film capacitors having linear capacitance values over a wide bias voltage and frequency range.

BACKGROUND OF THE INVENTION Currently, the wireless communications and related industries require capacitors that operate at high frequencies with low loss and have capacitance values that are essentially independent of the corresponding bias voltage. Discrete capacitors have such characteristics and are typically used in these industries as vias and feedthrough capacitors, as well as capacitors for switched capacitor filters. Thin film capacitors are desirable in these industries because of their low manufacturing cost, small size, and uncomplicated wire connections. However, currently available thin film capacitors have undesirably large and other properties that hinder their use in such industries.

A typical thin film capacitor has a parallel plate capacitor structure formed on an integrated circuit semiconductor chip with a thin film of dielectric material sandwiched between top and bottom plates. In conventional metal-oxide-semiconductor (MOS) capacitors, the aluminum surface thin film is the top plate.
The bottom plate is a heavily doped n ⁺ region, which is formed during the emitter diffusion of the integrated circuit semiconductor. The capacitance value is directly proportional to the relative permittivity of the dielectric thin film, is proportional to the surface area of the capacitor, and is inversely proportional to the thickness of the dielectric thin film.

Thin film capacitors with SiO ₂ thin film dielectrics are well known to those skilled in the art and are currently used in many integrated circuits and certain wireless communication applications. However, Si
Since the relative permittivity of O ₂ is relatively low at about 3.9, these capacities are required to obtain a capacitance value of about nanofarads.
It also requires 70% of the active area of an integrated circuit chip. Thus, while these types of capacities are much smaller than individual capacities, they are still undesirably large for most wireless communication applications. For the thin film SiO ₂ capacity, please refer to JL McClear.
y), "Matching Characteristics of MOS Capacitance and Voltage and Temperature Dependence", IEEE Journal of Solid-State Circuits (IEEE J. of So)
lid-State Circuit), SC-16
Vol. 6, No. 6, pages 608-616 (December 1981). It is included here as a reference.

Barium titanate (BaTiO ₃ ) or barium strontium titanate (Ba _1-x Sr _x TiO 2).
₃ ) Compact thin film capacitors using high dielectric constant thin films are known. Ba _1-x Sr _x TiO ₃ thin film capacitors have been used in high density random access memory (DRAM). Ferromagnetic materials such as BaTiO ₃ typically have very high dielectric constants, on the order of 1000 or even higher, so capacitors made with this material tend to have very compact dimensions. . However, BaTiO ₃
And Ba _1-x Sr _x TiO ₃ thin film capacitors both show unfavorable voltage dependence, and their capacitance values depend on the bias voltage. BaTiO ₃ and Ba _1-x Sr _x TiO
_{3 For} thin film capacitors, see Q.X.J.
X. Jia) et al., "Ba TiO ₃ thin film capacitors deposited by RF magnetron sputtering," Thin Solid Films.
s), pp. 230-239 (1992) and T. Horikawa (T.Horikawa) et al., "was deposited by RF sputtering (Ba, Sr) dielectric properties of TiO ₂ thin film", Japan Journal Applied Physics (Japan J. Appl. Phys.) No. 32
Volume, Part 1, Issue 9B, 4126-4130 (199
September 3). These are included herein by reference. BaTiO ₃ further has a undesirably low roll-off frequency, with the result typically the case, high loss at frequencies above 10 MHz.

Non-thin film dielectric materials with relatively high high dielectric constant, low dielectric loss and good temperature stability have been used in the microwave industry to form microwave devices such as resonators and oscillators. There is. However, typically, microwave materials have not been used to form thin films or thin film capacitors. The processes used to form most microwave materials in thin films are not compatible with integrated circuit semiconductor processes. More specifically, 8
A temperature upper limit of 00 ° C. is typically imposed during semiconductor processing of integrated circuits, and microwave materials are required to form chemical structures with low loss of capacitance and low temperature coefficient.
Often requires high process temperatures above 1300 ° C. While certain additives promote compound formation at lower temperatures, the additives are often incompatible with semiconductor integrated circuit processes. Therefore, microwave dielectric materials have not been used to make thin film capacitors.

Ba ₂ Ti ₉ O ₂₀ is a dielectric resonance filter,
It has been developed for microwave devices such as microwave stripline circuits, various types of oscillators and phase shifters that are not thin film devices. This material has a relatively high dielectric constant, low dielectric loss and good temperature stability. Ba
For a more detailed discussion of the formation of ₂ Ti ₉ O ₂₀ and its use in microwave applications, see US Pat. No. 4,563,661.
No. 4,337,446 and 3,938,064
No. These have the same rights as the invention and are hereby incorporated by reference.

There is a need for a compact thin film capacitor that exhibits linear capacitance over a wide bias voltage range at high frequencies and that can be fabricated on conventional silicon integrated circuits at a relatively low cost.

SUMMARY OF THE INVENTION An integrated circuit in accordance with the present invention includes an active device such as a transistor electrically connected to a capacitor, where the capacitor uses a dielectric region that includes a thin film of Ba _x Ti _y O _z. .
X, Y and Z are about 2, 9 and 20, respectively. Such thin films have a relatively high dielectric constant of about 25-40. The capacitance further includes a first portion that sandwiches the dielectric thin film region.
And a second electrode. In one embodiment, the first electrode is disposed between the dielectric thin film region and the semiconductor substrate and acts as a barrier that essentially prevents chemical reactions between the dielectric thin film region and the semiconductor substrate material. For example, a suitable first electrode comprises a bilayer structure of tantalum under platinum.

The capacitance of the integrated circuit according to the invention has the advantageous properties of relatively compact dimensions, linear capacitance over a wide frequency and bias voltage range, low dissipation factor, very low leakage flux and high roll-off frequency. Have. For capacity applications, bypass and feedthrough capacitors and DRAMs
Also included is a switched capacitor capacitance for use in an integrated circuit of a wireless communication system. Additional features and advantages of the present invention will be more readily apparent from the following detailed description and the accompanying drawings.

DETAILED DESCRIPTION The present invention provides a Ba _x Ti _y O _z thin film in which the ratios of X, Y and Z values are approximately 2, 9 and 20 and can be deposited during the integrated circuit fabrication process to provide a capacitive dielectric. Based on the discovery that body regions can be formed. Such films have advantageous relatively high dielectric constants in the range 25-40.
As a result, the volume can have compact dimensions. These capacitors have the further advantageous property of having a substantially linear capacitance value. That is, it is essentially constant over a wide frequency and bias voltage range, has a very low leakage voltage of about 4 × 10 ⁻⁹ A / μm ^2, and has a roll-off frequency far exceeding 200 MHz. The capacitance value is usually -10 to +
In the bias voltage range of 10 V, it does not change to 1.6% or more, and the loss slope is about 0.0001.

A portion of an integrated circuit semiconductor chip 1 according to the present invention is shown in FIG. In the illustrated portion of the integrated circuit 1, a Ba _x T formed on a first active device 10 such as a conventional metal-oxide-semiconductor field effect transistor (MOSFET) and a substrate 15 such as a silicon substrate.
A capacitor 5 using a dielectric thin film of i _y O _z is included. Second
The drain region of transistor 20 is also shown. Specific forms of active devices include NMOS, PMOS or C
The use of either MOS is not critical to the practice of the invention, based on the desired operation of the integrated circuit. Other suitable active devices include, for example, bipolar junction transistors and GaAs MESFETs.

Transistors 10 and 20 are, for example, SMC, VLSI technology, 1
It can be made by conventional process methods, as described in detail in Chapter 1, pages 466-515 (Maglow Hill, 1988). This document is included here as a reference. In FIG. 1, transistors 10 and 20 include field oxide regions 25 and 30, which are formed of, for example, SiO ₂ and act as an insulator between adjacent devices such as transistor 10 and transistor 20. The source and drain regions 35 and 40 of the transistor 10 are formed by doping the NMOS with an n-type impurity such as arsenic or phosphorus. Transistor 1 with reduced source and drain resistance
An optional layer of silicide 45 is deposited on the source and drain regions 35 and 40 to allow more current to flow.

The gate 50 of the transistor 10 comprises polysilicon 55 doped with n-type impurities, for example by implantation or vapor phase doping. Gate polysilicon 5
5 is placed on the SiO ₂ spacer 60. Silicide 6
The optional layer 2 is also deposited on the gate polysilicon 55 in order to reduce the electrical resistance of the gate 50. An insulating layer 65, for example P-glass, which is a phosphorus-doped oxide, is then deposited over transistors 10 and 20 to protect transistors 10 and 20 and facilitate electrical connection. The electrode window 66 is etched into the insulating layer 65 to expose the device gate 50 and source and drain regions such as regions 35 and 40. In the cross section of the integrated circuit in FIG. 1, only the drain regions of the transistors 10 and 20 are exposed, but outside the cross section shown, in other regions of the integrated circuit 1, the gate and source are exposed. It will be easy to understand.

In a typical prior art integrated circuit fabrication method, aluminum is formed in a designated pattern to electrically connect the device through the etched regions and to other circuit elements in the desired fashion. Such a conductive interconnect layer is deposited on the surface of insulating layer 65. However, in accordance with the present invention, at least one capacitor 5, such as capacitor 5 shown in FIG. 1, is formed on the integrated circuit, such as insulating layer surface 67, prior to forming the interconnect layer.

The capacitor 5 has a first electrode 70 formed on the surface 67 of the insulating layer and a Ba _x T deposited on the first electrode 70.
The dielectric thin film region 75 of i _y O _z , and the second electrode 80 facing the first electrode 70 formed on the dielectric thin film region 75.
including. It is possible that the first electrode 70 has a two-layer structure. Such a structure is, for example, a platinum layer formed on a tantalum layer. Platinum is a suitable electrode material, but it undergoes deleterious chemical reactions with silicon.
As a result, a diffusion barrier, such as tantalum, is used as the second electrode layer, which contacts the insulating layer surface 67 and essentially prevents chemical reactions between the platinum and the silicon of the substrate 15.
A suitable thickness for each layer of the bilayer structure is 0.01 to 0.5.
It is in the range of μm.

Further, the first electrode 70 is made of tantalum, platinum,
It is possible to have a single layer structure of a conductive material containing palladium, titanium nitride or a ruthenium compound. Suitable overall thickness of the first electrode 70, whether in a single layer or double layer structure, is in the range of about 0.1 to 0.5 μm. 0.1
A thickness of less than μm is not preferable because of high electric resistance.
On the other hand, a thickness of 0.5 μm or more is generally disadvantageous because the manufacturing cost is high and the adhesion is poor. The first electrode 70 is larger than the second electrode 80 in order to make electrical connection to the first electrode 70 in the manner described in detail below.

The deposited Ba _x Ti _y O _z dielectric thin film regions have x, y and z values such as Ba ₂ Ti ₉ O ₂₀ .
It has a stoichiometric composition in the ratio of approximately 2, 9, 20. The mole fractions of Ba and Ti in the dielectric thin film 75 are each 1
0% to 20% and correspondingly 90% to 80
Should be%. Dielectric thin film region 75 should have a thickness in the range of approximately 50 to 150 nm. 50 nm
The following thickness is not preferred due to dielectric breakdown. Fifteen
A thickness of 0 nm or more is generally disadvantageous because it requires a larger surface area because the capacity per unit area is lower than the capacity for obtaining a specific capacity value. A typical area required for a capacitance using a Ba ₂ Ti ₉ O ₂₀ thin film with a relative permittivity of 35 and a thickness of 70 nm is 44 p.
To obtain a capacitance in the range of F to 1.1 nF, 10
It will be between 0 × 100 μm and 500 × 500 μm. Capacities less than 10 ⁴ μm ² are undesirable because the resulting capacitance values are too small for most integrated circuit applications.

Suitable deposition processes for forming the dielectric thin film region 75 include, for example, radio frequency (RF) magnetron sputtering, CVD, vacuum deposition, laser ablation and sol-gel. A suitable Ba ₂ Ti ₉ O ₂₀ ceramic source for RF magnetron sputtering is
It can be produced by a known technique. For more details on suitable methods for producing Ba ₂ Ti ₉ O ₂₀ , see US Pat. Nos. 4,563,661, 4,337,446, cited above.
And No. 3,938,064. RF
A method of forming a Ba ₂ Ti ₉ O ₂₀ target for depositing a dielectric thin film by magnetron sputtering is described below with respect to an example of making a capacitor in an integrated circuit according to the present invention.

It is possible that the dielectric thin film region 75 has an amorphous or polycrystalline structure, while having a relatively high dielectric constant in the range of about 25-40. The term polycrystalline is meant to include crystalline forms of a dielectric that vary in size, shape and crystal structure. The presence of the crystal layer in the thin film region 75 can be determined by using X-ray diffraction. It is possible to crystallize in the dielectric region 75 by bringing the thin film region to a temperature of about 650 ° C. At such temperatures, the thin film regions 75 may have a microstructured surface and a dielectric constant in the range of about 30-40. Also, since aluminum can melt at temperatures of 650 ° C., such dielectric thin film regions 75 should be formed prior to the formation of the aluminum interconnect layer.

Essentially amorphous dielectric thin film region 7
5 produces an advantageous dielectric constant in the range of about 25 to 35. The range of such a dielectric constant is amazing considering the above-mentioned polycrystalline thin film region 75. The essentially amorphous dielectric thin film region 75 can be formed using low temperature deposition techniques at temperatures on the order of about 400-500 ° C. Further, such temperatures produce a dielectric thin film region 75 having an essentially smooth surface. X-ray diffraction can be used to detect the essentially absence of a crystalline layer in region 75.

Furthermore, it is possible according to the invention to bring the dielectric thin film region 75 to a temperature above 650 ° C. so as to increase the crystalline layer and produce a relatively large dielectric constant. However, such temperatures can have a detrimental effect on the adhesion and reaction between electrode 70 and substrate 15 when using conventional integrated circuit process technology.

The Ba ₂ Ti ₉ O ₂₀ dielectric material is approximately 5 pp.
It has a low temperature coefficient (Tcc) of m / ° C.
However, if a large or negative TCC is required, one generally replaces some of the titanium in the dielectric with tin or, as detailed in U.S. Pat. No. 4,563,661, cited above, titanium is used. The Ba ₂ Ti ₉ O ₂₀ can be changed by using a small amount or an excessive amount.

Suitable conductive materials for the second electrode 80 deposited on the dielectric thin film region 75 include, for example, aluminum, platinum, tantalum, palladium, titanium nitride or gold. As with the first electrode 70, a suitable thickness for the second electrode 25 is in the range of about 0.1 to 0.5 μm. The second electrode 25 can also have a two-layer structure such as gold on titanium. Suitable thicknesses for such a two-layer structure are 0.1 to 1 μm for titanium and 0.1 to 0.5 μm for gold.
m. The first and second electrodes 70 and 80 are 2
It may be any of various materials having an electric resistance of Ω / □ or less and compatible with the process method of the corresponding integrated circuit.

According to the invention, after the formation of the capacitor 10, when the interconnection layer is formed, the end region 9 of the capacitor 5 is prevented in order to prevent a short circuit between the first and second capacitor electrodes 70 and 80.
An insulating material such as SiO ₂ is deposited on 0, 91 and 92. Next, an interconnect layer 95 is formed on the insulating layer 65 and the corresponding electrode windows 66 are etched in order to electrically connect the devices 10 and 20 and the capacitor 5 in the desired manner. Suitable materials for interconnect layer 95 include aluminum and copper. In the integrated circuit 1, the drain of the transistor 10 is electrically connected to the first electrode 70 of the capacitor 5, and the second electrode 80 of the capacitor is connected to the transistor 2 of the capacitor 2.
It is electrically connected to the 0 source.

The materials 30 and 35 used for interconnection are not critical to the practice of the present invention, and the same materials 15 and 25 used for the capacitive electrodes are convenient and are typical of those used in integrated circuit processes. The conductive material may be used. Thus, it is possible for the first interconnect layer to form the first electrode and to be the electrical interconnect between the integrated circuit elements. Similarly, the second interconnect layer can be another circuit element interconnect to form the second electrode of the capacitor. In such an embodiment, it is appropriate to use an insulating material such as SiO ₂ to prevent short circuits where the first and second interconnect layers overlap each other. In another similar embodiment, the first interconnect layer is a two-layer first
Serves as one layer of the electrode structure.

The specific process for forming active devices and capacitors described above is for purposes of illustration only and not for the purpose of limiting the invention. It will be readily apparent to those skilled in the art that other device and capacitor fabrication techniques can be used to produce the integrated circuit according to the present invention. Furthermore, the capacitor 5 shown in FIG. 1 is in the form of parallel plates for the purposes of illustration only. Capacitors according to the present invention can have a coplanar structure, a tab capacitor structure or a corrugated structure. Furthermore, it is possible to form capacitors in different regions of the integrated circuit, such as on a second or higher insulating layer, when using, for example, multi-layer interconnects and insulating layers. Also, the capacitors can be formed in tabs or other integrated circuit areas within the substrate.

[0028] was prepared an example of a thin film capacitor having example Ba ₂ Ti ₉ O ₂₀ dielectric thin film capacitor having a Ba ₂ Ti ₉ O ₂₀ dielectric on integrated circuit semiconductor. The thickness of the dielectric thin film is about 1
At 40 nm, the measured dielectric constant was about 40. -1
D. of 0V to 10V. C. The measured normalized change in capacitance (ΔC / C) of the fabricated example over zero volt bias over voltage range is shown in FIG.
As shown in FIG. 2, each of the manufactured examples has a value of 0.
The maximum positive and negative relative capacitance changes of 002 and -0.014 were shown. As a result, the manufactured example has 1.6% ([0.002+
An excellent overall relative change of 0.014] × 100) or less was achieved.

During the fabrication of the thin film capacitor, a silicon wafer substrate having a diameter of 10 cm was used. The wafer includes a first metallized electrode layer, which consists of a bilayer structure of tantalum on platinum. The non-metallized bottom of the substrate was held in the chamber by a 9 cm diameter stainless steel ring forming one side of a 3000 W quartz lamp heater. The substrate was held on the annulus by spring clips. A 6 cm diameter Ba ₂ Ti ₉ O ₂₀ ceramic target was placed 8 cm on the electrode surface of the substrate. In order to sputter the material and deposit it on the electrode substrate surface, Ba ₂ Ti
_The radio frequency signal was directed at a ₉ O ₂₀ target. The target was pre-sputtered for about 10 minutes before deposition.

During Ba ₂ Ti ₉ O ₂₀ deposition, the sputtering parameters were: substrate temperature, gas pressure, Ar / O ₂ ratio, RF
Power and substrate bias voltage. The bottom of the substrate is 400 ° -700 ° C due to direct radiation from the lamp heater.
Was heated to a temperature in the range. About 30 to 60 mTorr
An atmosphere of Ar and O ₂ at a pressure of about 2 to 1 was maintained in the deposition chamber. The RF magnetron voltage was 3 Kv, the plate current was 130 mA, and the net power was 150 W. Sputtering was performed for 70 minutes to obtain a dielectric thin film of 140 nm.

The heating of the substrate for the deposition process was rapid, on the order of 5 minutes, while the substrate was cooled to below 200 ° C. for several hours. The Ar and O ₂ atmosphere was maintained during cooling to 400 ° C. The substrate has a D.V. of 10V. C. A bias was applied, but the effect was not clear.

Next, a second electrode having a bilayer structure of 100 nm titanium under 200 nm gold was formed on the top surface of the dielectric of 474 μm × 474 μm area using a conventional electron beam evaporation process. did. The resulting capacitance had a capacitance value of 0.56 nF.

Ba ₂ Ti ₉ used during fabrication of thin film capacitor example
The O ₂₀ ceramic target was prepared as follows. High purity BaTiO ₃ (HPB grade) both available from TAM Ceramics, Niagara Falls, NY
And TiO ₂ (TAM # 59030-lot 8135)
The powder was combined with 1 kg of a mixture having the formula BaTiO ₃ +4.42 TiO ₂ . The mixture powder was mill mixed for 16 hours under water in ZrO ₂ medium with 2 weight percent dispersant. The dispersant used was R. T. Durban Dispersant No. 821A, available from Vanderbilt, Norwalk, Connecticut. The combination was then filtered, dried and granulated through a 50 mesh screen to make a powder. Next, this powder was pre-reacted for 6 hours at 1135 ° C. in an oxygen atmosphere.

Next, the previously reacted powder is Zr.
A second mill mix was performed under water in O ₂ medium for 9 hours. The resulting material was filtered again, dried and granulated through a 50 mesh screen to form a second powder. 450 g of the second powder was isostatically pressed at 25,000 psi and sintered at 1390 ° C. for 12 hours in an oxygen atmosphere to form a cylinder having a diameter of 6 cm. Next, the obtained cylinder is further subjected to 1 at 1150 ° C. in an oxygen atmosphere.
Annealed for 2 hours to produce a Ba ₂ Ti ₉ O ₂₀ sintered cylinder.

A thin piece of about 2 mm was cut out from the sintered cylinder and mounted on a copper back plate with indium solder to form a Ba ₂ Ti ₉ O ₂₀ target. Target had a density of 96-99%, a substantially single phase microstructure of _{98% Ba 2 Ti 9 O 20} . The measured microwave loss of the ceramic is Q = 9000 at 4.5 GHz.
2 × 1 in the temperature range of -20 ° to 60 ° C.
It had a temperature coefficient of resonance frequency of 0 ^-6 / ° C. The method used to calculate the mixture produces a barium-rich compound,
The stoichiometric composition results from the actual analysis of the raw materials and the loss of barium during the dielectric process.

While one embodiment of the invention has been described in detail, many modifications are possible without departing from the guidelines. All such modifications are considered to be within the scope of the claims. For example, metal-insulator-metal (MI
Although M) type capacitors are depicted in FIG. 1, it should be understood that they include metal-insulator-semiconductor (MIS) thin film capacitors and that various other thin film capacitor morphologies and molds can be produced in accordance with the present invention. is there.

The form of the MIS capacitor is the MI shown in FIG.
Essentially similar to the M-capacitor configuration, except that the first electrode 70 is not formed of metal, but is part of the substrate 15 heavily doped with n-type impurities to act as a conductor. . Since the interface between the Ba _x Ti _y O _z dielectric region 75 and the metal first electrode has low resistance and better conductivity than the heavily doped semiconductor electrode, the MIM type capacitance is typically a corresponding MIS type capacitor. It has a higher roll-off frequency than the capacity. Therefore, such MIM capacitors would be more suitable for high frequency circuits.

[Brief description of the drawings]

1 is a cross-sectional view of an example of an active device and a linear thin film capacitor in an integrated circuit according to the present invention.

FIG. 2 is a diagram showing a graph of relative changes in bias voltage versus capacitance for an example of manufacturing the thin film capacitor in FIG.

[Explanation of symbols]

 1 semiconductor chip, integrated circuit 5 capacitance 10 active device, transistor 15 substrate, material 20 transistor 25,30 field oxide region, material 35 source region, material 40 drain region 45 silicide 50 gate 55 polysilicon 60 spacer 65 insulating layer 66 for electrode Window 67 Insulating layer surface 70 Electrode 75 Dielectric region, dielectric thin film region 80 Electrode 85 Insulating material 90, 91, 92 Edge region 95 Interconnect layer

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Roderick Kent Watts United States 07901 New Jersey, Summit, Oak Knorr Road 14

Claims (21)

[Claims] 1. An active device; and a capacitor electrically connected to the active device, the capacitor having a dielectric region sandwiched between first and second conductive electrodes, the dielectric region being An integrated circuit comprising a thin film of Ba _x Ti _y O _z having an essentially polycrystalline structure, wherein the values of x, y and z are in the ratio of approximately 2, 9 and 20. 2. The integrated circuit of claim 1 wherein the region comprises Ba in a mole fraction of 10% to 20% and Ti in a corresponding mole fraction of 90% to 80%. 3. The integrated circuit of claim 1, wherein the dielectric region has a thickness between the first and second electrodes in the range of approximately 50 to 150 nm. 4. The integrated circuit according to claim 3, wherein the thickness of the dielectric region is 100 nm or more. 5. The integrated circuit according to claim 1, wherein the first electrode is formed on the insulating layer of the semiconductor chip. 6. The integrated circuit according to claim 1, wherein the first electrode is a barrier for essentially preventing a chemical reaction between the semiconductor substrate material of the integrated circuit and the dielectric thin film. 7. The integrated circuit according to claim 6, wherein the first electrode has a two-layer structure of tantalum under platinum. 8. The integrated circuit of claim 1, wherein the capacitor has a metal-insulator-metal configuration. 9. The integrated circuit according to claim 1, wherein the capacitor has a parallel plate structure. 10. Forming a first electrode; on said first electrode in a dielectric region comprising a thin film of Ba _x Ti _y O _z , wherein the values of x, y and z are in the ratio of approximately 2, 9, 20. And forming a second electrode on the dielectric thin film facing the first electrode, the method for forming an integrated circuit capacitor on a semiconductor substrate. 11. The step of forming a dielectric region further comprises Ba _x
The method of claim 10 including depositing a thin film by a radio frequency magnetron using a Ti _y O _z target. 12. A first electrode is formed on a region of the integrated circuit and the integrated circuit having the first electrode is brought to a temperature in the range of 400 ° to 650 ° C. during the deposition of the Ba _x Ti _y O _z thin film. The method of claim 10, further comprising the steps of: 13. The method of claim 12, wherein the step of heating the integrated circuit further comprises the step of heating to said temperature for about 3 to 10 minutes and allowing the heated integrated circuit to cool for several hours after deposition. 14. The method of claim 10, further comprising forming the dielectric region in an atmosphere of Ar and O ₂ . 15. The step of forming a dielectric region comprises Ar /
Further method of claim 14 comprising maintaining O ₂ to about 30 atmosphere pressure range of 50 mTorr. 16. The method of claim 10, wherein the polycrystalline structure is obtained by the step of annealing the dielectric region. 17. The first electrode is formed on a region of the integrated circuit and further comprises forming a barrier to essentially prevent chemical reactions between the material of the integrated circuit and the dielectric region. the method of. 18. The step of forming a first electrode further comprises forming a bilayer structure of platinum and tantalum, wherein tantalum contacts the area of the integrated circuit and platinum contacts the dielectric area. the method of. 19. The integrated circuit of claim 1, wherein the dielectric region comprises an essentially amorphous structure. 20. The method of claim 10, wherein the dielectric region comprises an essentially amorphous structure. 21. The formed dielectric region has a molar fraction of Ba of 10% to 20% and a corresponding 90% to 8%.
The method of claim 10 comprising 0% mole fraction of Ti.