KR970003732A - Pad of semiconductor device and manufacturing method thereof - Google Patents

Pad of semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
KR970003732A
KR970003732A KR1019950017264A KR19950017264A KR970003732A KR 970003732 A KR970003732 A KR 970003732A KR 1019950017264 A KR1019950017264 A KR 1019950017264A KR 19950017264 A KR19950017264 A KR 19950017264A KR 970003732 A KR970003732 A KR 970003732A
Authority
KR
South Korea
Prior art keywords
pad
semiconductor device
pattern
protective layer
wiring layer
Prior art date
Application number
KR1019950017264A
Other languages
Korean (ko)
Other versions
KR0155837B1 (en
Inventor
김용식
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950017264A priority Critical patent/KR0155837B1/en
Publication of KR970003732A publication Critical patent/KR970003732A/en
Application granted granted Critical
Publication of KR0155837B1 publication Critical patent/KR0155837B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

패드 상부에 형성된 보호층의 식각여부를 판별할 수 있는 판별 패턴을 구비하는 반도체 장치의 패드 및 그 제조방법에 관하여 기재되어 있다. 본 발명에 따른 반도체 장치의 패드는 반도체기판, 상기 반도체기판 상에 형성된 배선층, 상기 배선층 상에 형성되고, 와이어 본딩시 와이어가 접촉될 부분의 상기 배선층을 노출시키는 패드가 형성된 보호층을 구비하며,이때 상기 패드는 상기 패드의 모서리에 상기 보호층의 식각 여부를 판별할 수 있는 판별 패턴을 구비하는 것을 특징으로한다.Disclosed is a pad of a semiconductor device having a discrimination pattern capable of discriminating whether a protective layer formed on the pad is etched and a method of manufacturing the same. The pad of the semiconductor device according to the present invention includes a semiconductor substrate, a wiring layer formed on the semiconductor substrate, a protective layer formed on the wiring layer, and having a pad formed thereon to expose the wiring layer of a portion to which the wire is to be contacted during wire bonding, At this time, the pad is characterized in that it has a determination pattern for determining whether the protective layer is etched in the corner of the pad.

따라서, 고집적화된 반도체 장치의 패드 에치 불량을 방지하여 와이어와 배선층 간의 접촉저항의 증가를 방지할 수 있으며, 신뢰성 있는 반도체 장치를 제공할 수 있고, 반도체 장치의 제조수율을 증가시킬 수 있다.Therefore, it is possible to prevent the pad etch defect of the highly integrated semiconductor device, to prevent the increase of the contact resistance between the wire and the wiring layer, to provide a reliable semiconductor device, and to increase the manufacturing yield of the semiconductor device.

Description

반도체 장치의 패드 및 그 제조방법Pad of semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 일 실시예에 따라 제조된 반도체 장치의 패드 부분을 도시한 평면도.3 is a plan view illustrating a pad portion of a semiconductor device manufactured according to an embodiment of the present invention.

Claims (11)

반도체기판; 상기 반도체기판 상에 형성된 배선층; 상기 배선층 상에 형성되고, 와이어 본딩시 와이어가 접촉될 부분의 상기 배선층을 노출시키는 패드가 형성된 보호층을 구비하는 반도체 장치에 있어서, 상기 패드는 상기 패드의 모서리에 상기 보호층의 식각 여부를 판별할 수 있는 판별 패턴을 구비하는 것을 특징으로 하는 반도체 장치.Semiconductor substrates; A wiring layer formed on the semiconductor substrate; A semiconductor device having a protective layer formed on the wiring layer and having a pad for exposing the wiring layer of a portion to which wire is to be contacted during wire bonding, wherein the pad determines whether the protective layer is etched at an edge of the pad. A semiconductor device comprising a discrimination pattern that can be formed. 제1항에 있어서, 상기 판별 패턴은 상기 보호층과 동일한 물질층으로 형성된 것을 특징으로 하는 반도체장치.The semiconductor device of claim 1, wherein the discrimination pattern is formed of the same material layer as the passivation layer. 제1항에 있어서, 상기 판별 패턴은 와이어 본딩을 방해하지 않는 크기로 형성된 것을 특징으로 하는 반도체 장치.The semiconductor device of claim 1, wherein the determination pattern is formed to a size that does not interfere with wire bonding. 제1항에 있어서, 상기 판별 패턴은 상기 패드 모서리에 삼각형 형태로 형성된 것을 특징으로 하는 반도체장치.The semiconductor device of claim 1, wherein the discrimination pattern is formed in a triangular shape at an edge of the pad. 제1항에 있어서, 상기 판별 패턴은 상기 패드가 둥근 형태를 가지도록 상기 패드의 모서리에 형성된 것을 특징으로 하는 반도체 장치.The semiconductor device of claim 1, wherein the determination pattern is formed at an edge of the pad such that the pad has a rounded shape. 제1항에 있어서, 상기 판별 패턴은 상기 패드가 오각형, 육각형, 십자형 중에서 선택된 어느 하나의 형태를 가지도록 상기 패드의 모서리에 형성된 것을 특징으로 하는 반도체 장치.The semiconductor device of claim 1, wherein the determination pattern is formed at an edge of the pad such that the pad has any one selected from a pentagon, a hexagon, and a cross. 제4항 내지 제6항의 어느 한 항에 있어서, 상기 판별 패턴은 상기 패드의 모서리 중 일부 모서리에 형성된 것을 특징으로 하는 반도체 장치.The semiconductor device according to any one of claims 4 to 6, wherein the discrimination pattern is formed at a part of corners of the pad. 반도체 기판 상에 배선층을 형성하는 단계; 상기 배선층 상부에 보호층을 형성하는 단계; 상기 보호층 상부에 포토레지스트를 도포한 다음, 패터닝하여 포토레지스트 패턴을 형성하는 단계; 및 상기 포토레지스트 패턴을 식각 마스크로 사용하여 상기 보호층을 식각하여 패드를 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 제조방법에 있어서, 상기 패드는 상기 포토레지스트 패턴에 의해 그 모서리가 제거된 사각형 형태로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.Forming a wiring layer on the semiconductor substrate; Forming a protective layer on the wiring layer; Applying a photoresist on the protective layer and then patterning the photoresist to form a photoresist pattern; And forming a pad by etching the protective layer using the photoresist pattern as an etching mask, wherein the edge of the pad is removed by the photoresist pattern. The semiconductor device manufacturing method characterized in that it is formed in a rectangular shape. 제8항에 있어서, 상기 제거된 모서리 부분을 상기 패드 상부 보호층의 식각 여부를 판별하는 판별 패턴으로 사용하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 8, wherein the removed edge portion is used as a discrimination pattern for determining whether the pad upper protective layer is etched. 제8항에 있어서, 상기 패드는 그 모서리가 둥근 형태를 갖도록 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 8, wherein the pad is formed to have a rounded corner. 제8항에 있어서, 상기 패드는 육각형 형태로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 8, wherein the pad is formed in a hexagonal shape. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017264A 1995-06-24 1995-06-24 A pad of a semiconductor apparatus and its manufacturing method KR0155837B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950017264A KR0155837B1 (en) 1995-06-24 1995-06-24 A pad of a semiconductor apparatus and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950017264A KR0155837B1 (en) 1995-06-24 1995-06-24 A pad of a semiconductor apparatus and its manufacturing method

Publications (2)

Publication Number Publication Date
KR970003732A true KR970003732A (en) 1997-01-28
KR0155837B1 KR0155837B1 (en) 1998-12-01

Family

ID=19418152

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950017264A KR0155837B1 (en) 1995-06-24 1995-06-24 A pad of a semiconductor apparatus and its manufacturing method

Country Status (1)

Country Link
KR (1) KR0155837B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103199070A (en) * 2012-04-25 2013-07-10 日月光半导体制造股份有限公司 Semiconductor element with passivation segment and manufacturing method thereof

Also Published As

Publication number Publication date
KR0155837B1 (en) 1998-12-01

Similar Documents

Publication Publication Date Title
KR100652443B1 (en) Redistribution interconnection structure of wafer level package and the method for manufacturing thereof
KR950004464A (en) Manufacturing method of chip bump
JPH0621188A (en) Semiconductor wafer
KR930000226B1 (en) Semiconductor device and there manufacturing method protecting from pattern pollution
US4967259A (en) Wafer having a dicing area having a step region covered with a conductive layer and method of manufacturing the same
KR970003732A (en) Pad of semiconductor device and manufacturing method thereof
US4612274A (en) Electron beam/optical hybrid lithographic resist process in acoustic wave devices
KR980005930A (en) Semiconductor device and manufacturing method
KR100734250B1 (en) Bonding pad of semiconductor memory device for improving adhesive strength bonding pad and bonding wire and method of manufacturing the same
KR910020837A (en) Etching Process Method of Semiconductor Manufacturing Process
KR940010171A (en) Overlay vernier and its manufacturing method
KR920007191B1 (en) Manufacturing method of semiconductor elements
JPS63306635A (en) Method of marking semiconductor chip
KR960026867A (en) Manufacturing method of semiconductor device
KR970003731A (en) How to Form Pads on Metal Wiring of Semiconductor Devices
KR19990002944A (en) Scribe lanes in semiconductor devices
JPH04150043A (en) Semiconductor device
KR970013155A (en) Contact etching monitoring method for metal wiring
KR970030390A (en) A wafer structure for a semiconductor device
KR950019933A (en) Manufacturing method of semiconductor device
KR19990061124A (en) Semiconductor device
KR970052745A (en) Manufacturing method of semiconductor chip without inactivation layer in wafer
KR970053264A (en) Coded semiconductor chip and coding method
KR970053486A (en) Semiconductor Device Separation Method
KR960008979A (en) Method of forming alignment mark of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050607

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee