KR970003515A - Via contact formation method of semiconductor device - Google Patents

Via contact formation method of semiconductor device Download PDF

Info

Publication number
KR970003515A
KR970003515A KR1019950018893A KR19950018893A KR970003515A KR 970003515 A KR970003515 A KR 970003515A KR 1019950018893 A KR1019950018893 A KR 1019950018893A KR 19950018893 A KR19950018893 A KR 19950018893A KR 970003515 A KR970003515 A KR 970003515A
Authority
KR
South Korea
Prior art keywords
film
semiconductor device
etching
via contact
forming
Prior art date
Application number
KR1019950018893A
Other languages
Korean (ko)
Other versions
KR100367695B1 (en
Inventor
김종철
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950018893A priority Critical patent/KR100367695B1/en
Publication of KR970003515A publication Critical patent/KR970003515A/en
Application granted granted Critical
Publication of KR100367695B1 publication Critical patent/KR100367695B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Abstract

본 발명은 반도체 소자의 비아 콘택 형성방법에 관한 것으로, 반도체 소자의 다층금속 배선을 제조하는 공정중, 반도체 기판상부에 형성된 제1금속막과 제2금속막간의 연결을 위한 비아 콘택홀 형성시, 콘택홀 형성을 위한 감광막을 도포하기 전 단계에서 Si3N4박막을 도포하여 비아 콘택 형성 공정에서 감광막을 제거하기 위해 사용되는 O2플라즈마에 의해 SOG막이 수축되는 것을 방지함으로써, SOG 수축현상으로 인한 제2금속의 증착불량 및 단선과 콘택 프로파일의 열화를 방지하여 우수한 비아 콘택홀의 프로파일을 확보함과 아울러, 제2금속 증착의 공정마진을 확보하여 반도체 소자 제조수율을 향상시킬 수 있다.The present invention relates to a method for forming a via contact of a semiconductor device, and in the process of manufacturing a multilayer metal wiring of a semiconductor device, when forming a via contact hole for connection between a first metal film and a second metal film formed on a semiconductor substrate, In order to prevent the SOG film from contracting by the O 2 plasma used to remove the photoresist in the via contact forming process by applying the Si 3 N 4 thin film in the step before applying the photoresist for forming the contact hole, It is possible to secure a good via contact hole profile by preventing deposition failure of the second metal and deterioration of the disconnection and contact profile, and to improve the manufacturing yield of the semiconductor device by securing the process margin of the second metal deposition.

Description

반도체 소자의 비아 콘택 형성방법Via contact formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 기술에 따른 비아 콘택의 제조 공정도.2A-2D are process diagrams for the manufacture of via contacts in accordance with the teachings of the present invention.

Claims (5)

반도체 소자의 비아 콘택 형성방법에 있어서, 제1금속막 상부에 제1산화막과 평탄화 절연막 및 제2산화막을 순차적으로 형성하는 단계와, 상기 제2산화막의 상부에 제1산화막보다 얇은 두께의 Si3N4박막을 증착하는 단계와, 상기 Si3N|4박막 상부에 감광막을 증착하는 단계와, 상기 감광막을 노광 및 현상하여 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 사용하여 그 하부의 Si3N4박막의 소정부위를 검식식각하여 Si3N4으로 된 콘택 마스크를 형성하는 단계와, 상부에 잔류한 감광막을 제거하는 단계와, 상기 Si3N4으로 된 콘택 마스크를 이용하여 하부의 제2산화막을 습식식각으로 등방성 식각을 실시하는 단계와, Si3N4으로 된 콘택 마스크를 이용하여 하부의 SOG막과 제1산화막을 차례로 건식식각하여 하부면이 제1금속막이 되는 콘택홀을 형성하는 단계와, 전체 상부에 제2금속막을 증착하는 단계를 구비하는 것을 특징으로 하는 반도체 소자의 비아 콘택 형성방법.A method of forming a via contact of a semiconductor device, the method comprising: sequentially forming a first oxide film, a planarization insulating film, and a second oxide film on an upper portion of a first metal layer, and Si 3 having a thickness thinner than that of the first oxide layer on the second oxide layer; Depositing an N 4 thin film, and Si 3 N | 4) depositing a photoresist film on the thin film, exposing and developing the photoresist film to form a photoresist pattern, and using a photoresist pattern as a mask, by etching and etching a predetermined portion of the Si 3 N 4 thin film below Forming a contact mask of 3 N 4 , removing a photoresist film remaining on the upper portion, and performing isotropic etching of the lower second oxide film by wet etching using the contact mask of Si 3 N 4 . And dry etching the lower SOG film and the first oxide film in order using a contact mask made of Si 3 N 4 to form a contact hole in which the lower surface becomes the first metal film, and the second metal film over the entire upper part. And depositing the via contact. 제1항에 있어서, 상기 평탄화 절연막으로 SOG막인 것을 특징으로 하는 반도체 소자의 비아 콘택 형성방법.The method of claim 1, wherein the planarization insulating film is an SOG film. 제1항에 있어서, 상기 Si3N4박막형성시, 500℃ 이하의 온도에서 SiH4와 NH3가스를 사용하여 플라즈마를 이용한 CVD 방법으로 형성하는 것을 특징으로 하는 반도체 소자의 비아 콘택 형성방법.The method of claim 1, wherein the Si 3 N 4 thin film is formed by a CVD method using plasma using SiH 4 and NH 3 gas at a temperature of 500 ° C. or less. 제1항 또는 제3항에 있어서, 상기 Si3N4박막의 두께는 건식식각시 제1산화막과의 식각 선택비를 고려하여 800 ~ 1200A의 범위로 하는 것을 특징으로 하는 반도체 소자의 비아 콘택 형성방법.The semiconductor device of claim 1, wherein the thickness of the Si 3 N 4 thin film is in a range of 800 to 1200 A in consideration of an etching selectivity with the first oxide layer during dry etching. Way. 제1항에 있어서, 상기 Si3N4로 된 콘택 마스크를 사용하여 하부의 제2산화막을 습식식각할 시, HF 또는 BOE 용액을 사용하는 것을 특징으로 하는 반도체 소자의 비아 콘택 형성방법.The method of claim 1, wherein HF or BOE solution is used to wet etch the lower second oxide layer using the Si 3 N 4 contact mask. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950018893A 1995-06-30 1995-06-30 Method for forming via contact in semiconductor device KR100367695B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950018893A KR100367695B1 (en) 1995-06-30 1995-06-30 Method for forming via contact in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950018893A KR100367695B1 (en) 1995-06-30 1995-06-30 Method for forming via contact in semiconductor device

Publications (2)

Publication Number Publication Date
KR970003515A true KR970003515A (en) 1997-01-28
KR100367695B1 KR100367695B1 (en) 2003-02-26

Family

ID=37491169

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950018893A KR100367695B1 (en) 1995-06-30 1995-06-30 Method for forming via contact in semiconductor device

Country Status (1)

Country Link
KR (1) KR100367695B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100461838B1 (en) * 2002-10-16 2004-12-16 기아자동차주식회사 Shock-absorbing structure of a steering column for a vehicle
KR100542471B1 (en) * 1997-09-30 2006-03-23 지멘스 악티엔게젤샤프트 A dual damascene process for metal layers and organic intermetal layers
KR100777365B1 (en) * 2001-05-30 2007-11-19 매그나칩 반도체 유한회사 Method for forming a metal line

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100458476B1 (en) * 1997-12-27 2005-02-23 주식회사 하이닉스반도체 Method for forming metal interconnection of semiconductor device to improve filling characteristic of metal thin film and avoid generation of void

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62144342A (en) * 1985-12-19 1987-06-27 Oki Electric Ind Co Ltd Forming method of contact hole for multilayer interconnection
JPH0547941A (en) * 1991-08-19 1993-02-26 Clarion Co Ltd Forming method of multilayered wiring

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100542471B1 (en) * 1997-09-30 2006-03-23 지멘스 악티엔게젤샤프트 A dual damascene process for metal layers and organic intermetal layers
KR100777365B1 (en) * 2001-05-30 2007-11-19 매그나칩 반도체 유한회사 Method for forming a metal line
KR100461838B1 (en) * 2002-10-16 2004-12-16 기아자동차주식회사 Shock-absorbing structure of a steering column for a vehicle

Also Published As

Publication number Publication date
KR100367695B1 (en) 2003-02-26

Similar Documents

Publication Publication Date Title
KR100376628B1 (en) Conductive Interconnect Structure in Integrated Circuit and Method of Forming Conductive Interconnect
KR970003515A (en) Via contact formation method of semiconductor device
KR100325600B1 (en) a manufacturing method of contact holes of semiconductor devices
KR20040093565A (en) Method of manufacturing semiconductor device
KR100811258B1 (en) Method of fabricating the semiconductor device having WSix gate structure
KR100403350B1 (en) Method for forming borderless contact hole in a semiconductor device
US6284645B1 (en) Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process
KR100256809B1 (en) Method for forming contact hole in semiconductor device
KR100500936B1 (en) Method for forming contact hole
KR0122506B1 (en) Fabricating method for contact hole of semiconductor device
KR100439027B1 (en) Method for Forming Self-Align Contact
KR20050073043A (en) Method for forming bit line of semiconductor device
KR100328829B1 (en) Manufacturing method for contact in semiconductor device
KR950002192B1 (en) Contact structure and manufacturing method of semiconductor device
KR100298427B1 (en) Method for fabricating semiconductor device
KR960008563B1 (en) Fine contact hall forming method of semiconductor using double spacer
KR20060038597A (en) Method for forming pattern of semicondutor device
KR20030092525A (en) Method of manufacture contact hole in semiconduct device
KR970052262A (en) Contact hole formation method of semiconductor device
KR20020074581A (en) Method for forming capacitor of semiconductor device
KR20030000950A (en) Method for manufacturing semiconductor device
KR20010061121A (en) A method for forming a conductive line of a semiconductor device
KR970030663A (en) Method of manufacturing semiconductor device having planarized interlayer insulating film
KR970052486A (en) Method of forming contact window having sidewall oxide film
KR20010073646A (en) Method for eliminating polysilicon stringer and method for forming a storage node of a capacitor in semiconductor device with the eliminating method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20101125

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee