KR970003470A - Method of manufacturing silicon electrode - Google Patents

Method of manufacturing silicon electrode Download PDF

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Publication number
KR970003470A
KR970003470A KR1019950016039A KR19950016039A KR970003470A KR 970003470 A KR970003470 A KR 970003470A KR 1019950016039 A KR1019950016039 A KR 1019950016039A KR 19950016039 A KR19950016039 A KR 19950016039A KR 970003470 A KR970003470 A KR 970003470A
Authority
KR
South Korea
Prior art keywords
oxide film
temperature
manufacturing
tube
silicon
Prior art date
Application number
KR1019950016039A
Other languages
Korean (ko)
Inventor
임찬
홍병섭
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950016039A priority Critical patent/KR970003470A/en
Publication of KR970003470A publication Critical patent/KR970003470A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 실리콘 전극의 소자 제조 방법에 관한 것으로, 반도체 소자의 제조방법에 있어서, 비정질의 실리콘 배선을 형성한 다음, 실리콘 배선의 표면에 산화막을 형성하기 위해 약 600℃ 이하의 산화막 형성 튜브내로 웨이퍼를 투입하고 튜브의 온도를 서서히 약 850℃ 이상까지 상승시킴으로써, 실리콘층내에 핵의 생성을 최대한 억제하여 비저항의 값을 최소로 하는 잇점을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a device for a silicon electrode, wherein the method for manufacturing a semiconductor device comprises forming amorphous silicon wiring, and then wafer into an oxide film forming tube of about 600 ° C. or less to form an oxide film on the surface of the silicon wiring. The temperature of the tube is gradually increased to about 850 ° C. or more, thereby providing the advantage of minimizing the value of the specific resistance by maximizing the generation of nuclei in the silicon layer.

Description

실리콘 전극의 제조 방법Method of manufacturing silicon electrode

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 실시예에 의해 워드라인 표면에 산화막을 형성할 때 시간에 대한 온도의 변화를 도시한 그래프도, 제3도는 산화막 형성 튜브로 웨이퍼를 투입할 시의 온도따라 워드라인의 비저항이 달라지는 것을 도시한 상태표.2 is a graph showing a change in temperature with respect to time when an oxide film is formed on a surface of a word line according to an embodiment of the present invention. State table showing this change.

Claims (3)

반도체 소자 제조의 제조방법에 있어서, 반도체 기판에 게이트 산화막을 형성하고, 그 상부에 비정질 실리콘으로 된 워드라인을 형성하는 단계와, 600℃ 이하의 온도를 갖는 산화막 튜브로 웨이퍼를 투입하고, 서서히 온도를 상승시키는 단계와, 약 850℃ 이상의 온도에서 상기 워드라인 표면에 소오스, 드레인 이온 주입시 장벽층으로 사용되는 산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 실리콘 전극의 제조 방법.In the method of manufacturing a semiconductor device, a step of forming a gate oxide film on a semiconductor substrate, forming a word line of amorphous silicon on top thereof, and injecting a wafer into an oxide tube having a temperature of 600 ° C. or less, and gradually And forming an oxide film which is used as a barrier layer when source and drain ions are implanted on the surface of the word line at a temperature of about 850 ° C. or more. 제1항에 있어서, 상기 튜브의 온도 상승률이 분당 5℃ 이하로 하는 것을 특징으로 하는 실리콘 전극의 제조 방법.The method of manufacturing a silicon electrode according to claim 1, wherein the temperature increase rate of the tube is 5 ° C or less per minute. 제1항에 있어서, 상기 실리콘 배선을 PH3, PH3/N2, PH3/SiH4가스에서 580℃ 이하 온도로 증착한 것을 산화막 형성 튜브의 온도를 약 850℃ 이상까지 상승시켜 실리콘 배선의 표면에 산화막을 형성하는 것을 특징으로 하는 실리콘 전극의 제조 방법.The method of claim 1, wherein the deposition of the silicon wiring at a temperature of 580 ° C. or lower in PH 3 , PH 3 / N 2 , and PH 3 / SiH 4 gas is performed to raise the temperature of the oxide film forming tube to about 850 ° C. or higher. An oxide film is formed on the surface, The manufacturing method of the silicon electrode characterized by the above-mentioned. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950016039A 1995-06-16 1995-06-16 Method of manufacturing silicon electrode KR970003470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950016039A KR970003470A (en) 1995-06-16 1995-06-16 Method of manufacturing silicon electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950016039A KR970003470A (en) 1995-06-16 1995-06-16 Method of manufacturing silicon electrode

Publications (1)

Publication Number Publication Date
KR970003470A true KR970003470A (en) 1997-01-28

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950016039A KR970003470A (en) 1995-06-16 1995-06-16 Method of manufacturing silicon electrode

Country Status (1)

Country Link
KR (1) KR970003470A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980054454A (en) * 1996-12-27 1998-09-25 김영환 Polysilicon Cone Formation Method
KR20020043866A (en) * 2000-12-04 2002-06-12 류정열 Unitary type of ambient and air quality sensor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980054454A (en) * 1996-12-27 1998-09-25 김영환 Polysilicon Cone Formation Method
KR20020043866A (en) * 2000-12-04 2002-06-12 류정열 Unitary type of ambient and air quality sensor

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