KR970002714B1 - Atm physical layer subscriber access processor - Google Patents

Abstract

ATM physical class subscriber access processor includes: a transmitting cell processor(29) for receiving ATM cell from ATM hierarchy, and performing VC-4 pay load mapping; VC-4 generator(30) for generating VC-4(virtual container-4) signal; a pointer generator(7) for mapping a transmitting VC-4 signal to STM-1 frame; a frame generator(31) for generating STM-1 frame; a frame terminator(34) for processing a STM-1 frame; a pointer discriminator/processor(21) for detecting VC-4 signal from STM-1 frame; VC-4 terminator(33) for processing an error detection information and an overhead information; a receiving cell processor(32) for outputting ATMcell to ATM hierarchy; a connector(28) for connecting between the above elements(21,29-34) and the CPU. Accordingly, the ATM physical class subscriber access processor real-time processes a data error, accumulates all statistic errors generated on a transmission line path, and includes ATM cell by using asynchronous method without regard to a service speed of ATM cell.

Description

ATM physical layer subscriber access handler

1 is a block diagram of the present invention.

* Explanation of symbols for main parts of the drawings

1: transmission cell first-in, first-out part 2: cell speed matching part

3: cell payload scrambling unit 4: HEC (Header Error Control) calculation unit

5 transmission POH processing unit 6 B3 parity calculation unit

7: AU-4 pointer value generator 8: transmit MSOH (Multiplex SOH) processing unit

9: B2 parity calculation unit 10: Transmission RSOH (Regenerator SOH) processing unit

11 parallel scrambling unit 12 B1 parity calculation unit

13,14: 2: 1 multiplexer 15: parallel leaf reamer

16: B1 parity error detection unit 17: parallel descrambling unit

18: receiving RSOH processing unit 19: B2 parity error detection unit

20: receiving MSOH processing unit 21: AU-4 pointer value analysis and processing unit

22: B3 parity error detection unit 23: Receive POH processing unit

24 cell boundary identification unit 25 cell payload descrambling unit

26: effective cell extraction and filtering unit 27: receiving cell first-in first-out

28 common CPU and alarm interface 29 transmitting ATM cell processing unit

30: VC-4 generator 31: STM-1 frame generator

32: receiving ATM cell processing unit 33: VC-4 termination

34: STM-1 frame termination

The present invention is an ATM Physical Layer Subscriber Access Processor (ASAH-P: ATM Subsciber Access) that performs sub-physical functions among B-ISDN subscriber access functions based on the Synchronous Digital Hierarchy (SDH) transmission scheme. Handler-Physical: (hereinafter referred to as "ASAH-P").

Conventional Asynchronous Transfer Mode (ATM) physical layer subscriber access processors are referred to as Section Overhead (SOH) and Path Overhead (POH). ) Can be processed by a separate external processing device or a combination of several control signals in order to find the location of each byte. Busy. In addition, the clock extracted from the same clock source is used for the ATM function and the ATM physical layer subscriber access processor.

However, the conventional ATM physical layer subscriber access processor as described above requires a separate external processing device and a clock divider for interval overhead and path overhead processing, and a clock failure in one device affects another device. There is this.

Accordingly, the present invention devised to solve the above problem divides the low-speed clocks for overhead processing inside the device, and separates the clock from other devices by using FIFO (First In First Out). The purpose is to provide an access handler.

In order to achieve the above object, the present invention outputs a signal indicating a write state (TXFULL) to the ATM layer, and input data TCDATA [7: 0], a clock (TCCLK) synchronized with the input data, and a parity signal. After receiving an ATM cell from the ATM layer and receiving a transmission clock from the outside according to a transmit parity signal and a transmit control signal TXENB, TXFSOC, the cell rate is matched, and then scrambling of the cell payload and HEC for the cell. Transmission cell processing means for calculating (Header Error Control) and mapping the VC-4 payload; Path Over Header (POH) A VC- connected to the outside through a serial signal and receiving an output of the transmission cell processing means and generating a VC-4 (Virtual Container-4) signal according to the transmission clock. 4 generating means: receives the output of the VC-4 generating means and generates a pointer byte (H1, H2) indicating the VC-4 starting point J1 in the STM-1 payload according to the transmission clock to transmit VC Pointer generating means for mapping a -4 signal to a STM-1 (Synchronous Transfer Mode-1) frame; It is connected to the outside by a transmission MSOH (Multiples SOH) serial signal and a transmission RSOH (Regenerator SOH) serial signal, and receives the output of the pointer generating means and receives information on a section overhead (SOH: Sectin Over Header) according to the transmission clock. Frame generation means for generating parallel data by multiplexing, multiplexing the parallel data with the received data input from the line side, and outputting transmission data to the line side; It is connected to the outside by receiving MSOH (Multiplex SOH) serial signal and receiving RSOH (Regenerator SOH) serial signal, and receives the parallel data and received data from the line side and detects information and error according to the external received clock. Frame termination means for processing information on a section overhead (SOH: Section Over Header); Pointer analysis and processing means for receiving the output of the frame termination means and extracting a VC-4 signal from a received STM-1 frame by interpreting pointer bytes (H1, H2) supporting a VC-4 start point according to the received clock; Path Over Header (POH) VC-4, which is connected to the outside as a serial signal, receives the output of the pointer analysis and processing means and processes information on error detection and path overhead according to the reception clock. Terminating means; Receives an operation enable signal (RCCLK) of the ATM layer and a receive enable signal (RXENB) indicating a data read state of the ATM layer, and receives an output of the VC-4 termination unit to identify a cell boundary according to the received clock. After descrambling the cell payload and extracting the valid cells, filtering is performed according to the control of the central controller to output data RCDATA [7: 0], a received parity signal as a parity signal, and a valid cell. Reception cell processing means for outputting a reception empty signal (RXEMPTY) signal indicating transmission and a reception cell start (RXSOC) signal indicating a start position of a cell to the ATM layer; And connection means for connecting the respective means and the central processing unit (CPU).

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a configuration diagram of the present invention, in which 1 is a first-in, first-out of a transmission cell, 2 is a cell rate matching unit, 3 is a cell payload scrambling unit, 4 is a HEC (Header Error Control) calculation unit, and 5 is a transmission PHO. A processor, 6 is a B3 parity calculator, 7 is an AU-4 pointer value generator, 8 is a transmit MSOH (Multiplex SOH) processor, 9 is a B2 parity calculator, 10 is a sender Regenerator SOH (RSOH) processor, 11 is parallel scrambling 12, B1 parity calculation unit, 13 and 14 2: 1 multiplexer, 15 parallel refraction unit, 16 b1 parity error detection unit, 17 parallel descrambling unit, 18 receiving RSOH processing unit, 19 B2 parity Error detection unit, 20 is a receiving MSOH processing unit, 21 is an AU-4 pointer value analysis and processing unit, 22 is a B3 parity error detection unit, 23 is a receiving POH processing unit, 24 is a cell boundary identification unit, 25 is a cell payload descrambling unit, 26 Is a valid cell extraction and filtering unit, 27 is a receiving cell first-in, first-out unit, and 28 is a common CPU and alarm inter E, where 29 is a transmitting ATM cell processing unit, 30 is a VC-4 (Virtual Container-4) generating unit, 31 is an STM-1 frame generating unit, 32 is a receiving ATM cell processing unit, 33 is a VC-4 termination unit, and 34 is an STM. -1 indicates the frame end portion, respectively.

In the description of the present invention, in accordance with the signal flow, the transmission direction will be described first and the reception direction will be described later. The transmission defines the direction in which the ATM cell is mapped to the STM-1 frame and transmitted on the line, and the reception is defined as the direction in which the ATM cell is extracted from the STM-1 frame. The transmitter transmits the cell connected through the transmit cell first-in-first-out unit 1 through the payload of VC4 in synchronization with an externally provided transmission clock (19.440 Mb / s). The receiving unit recovers the receiving cell by using a receiving clock provided from the outside and transmits the received cell to the receiving cell first-in-first-out operation 27.

The transmitting ATM cell processing unit 29 transmits the transmission data TCDATA [7: 0] in units of bytes, the transmission cell clock TCCLK synchronized with the transmission data, the transmission enable signal TXENB, which is a control signal, and the transmission cell start ( Upon receiving the ATM cell from the ATM layer according to the TXFSOC) signal and the TXPARITY signal, an error is detected in the common CPU and the information interface unit 28 when an error is detected. The transmit enable (TXENB) signal is a signal that the ATM layer sends data, and the transmit cell start (TXFSCO) signal indicates a start point of a cell. The ATM cell is received from the ATM layer through the transmit cell first-in-first-out unit 1 in an asynchronous manner, and the transmit ATM cell processing unit 29 receiving the transmit clock inserts an idle / unassigned cell. After matching the speed, it maps to the VC-4 signal payload through scrambling for the cell payload, header error control (HEC), and calculation for the cell. Also, a TXFULL signal indicating the write state of the transmission cell first-in-first-out part 1 is output to the ATM layer.

The transmitting ATM cell processing unit 29 is connected to a common CPU and an alarm interface unit 28, and transmit clock, transmit data TCDATTA, transmit cell clock TCCLK, transmit enable signal TXENB, transmit cell start ( The transmit cell is connected to a first transmit first-in first unit, a common CPU and an alarm interface unit 28 that receive a TXFSOC signal and a TXPARITY signal and output a TXFULL signal to an ATM layer. It is connected to the cell rate matching unit 2, the common CPU and the alarm interface unit 28 which receives the output of the first-in first-out unit 1 and the transmission clock, and inputs the output and transmission clock of the cell rate matching unit 2. It is connected to a receiving cell payload scrambling section 3, a common CPU and an alarm interface section 28, and has an HEC calculation section 4 which receives the output of the cell payload scrambling section 3 and a transmission clock. Detailed description is as follows.

The transmit cell first-in-first-out part 1 performs the temporal buffering function required to map cells from the ATM layer delivered asynchronously to the VC4 payload included on the Synchronous Digital Hierachy (SDH) transmission path, and thus the ATM layer. It provides a function to receive data in bytes by separating the operation clock of the physical layer and the operation clock of the physical layer. That is, the transmission cell first-in-first-out part 1 transmits a byte-by-byte transmission data TCDATA [7: 0] from the ATM layer, a transmission cell clock TCCLK synchronized with the transmission data, and a transmission enable signal TXENB as a control signal. And data is transmitted by a TX Cell Start (TXFSOC) signal. The transmit enable (TXENB) signal is the signal that ATM sends data and the transmit cell start (TXFSOC) signal indicates the cell's starting point. The write state outputs a TXFULL signal indicating a write availability state as '1' when there is at least one cell of four ATM cell buffers. At this time, the interface performance is monitored by receiving the transmit parity (TXPARITY) signal, which is an odd parity signal for the transmit data (TCDATA) in bytes, and the detected error accumulates in 8 bits and the CPU occurs when overflow occurs. An interrupt is generated. When the interrupt occurs, the transmission cell first-in-first-out unit 1 is reset or automatically reset by the CPU to generate up to four ATM cell losses. In addition, if the ATM cell from the ATM layer is larger or smaller than 53 octets due to other errors, the ATM cell is transferred to the CPU by interrupt method and the corresponding cell is lost.

The cell rate matching unit 2 performs a matching function between the cell transfer rate from the ATM layer and the cell transfer rate on the SDH transmission path, and the rate matching is any self-generating in the absence of an effective cell from the ATM layer at the cell transfer time. This is done by inserting cells, and idle cells are inserted by default. At this time, the header and payload values of the arbitrary cells to be inserted can be changed by the CPU.

The cell payload scrambling unit 3 performs a function of mixing the payload information of the cell with the unit of byte by using the self-synchronizing polynomial of X43 + 1, and can also be disabled by the CPU.

The HEC calculator 4 generates a CRC (Cyclic Redundancy Check) with the generated polynomial X ⁸ + X ² + X + 1 for the first 4 bytes of the cell header and inserts it into the 5th byte of the cell header. The generated polynomial may be disabled, and when disabled, the HEC information is transmitted without change. In addition, in order to improve the performance of the HEC inspection, a Coset function for performing an XOR (Exclusive OR) through the HEC information area in a "10110101" pattern and a disable function by the CPU are also performed. The first bit "0" of the pattern is the most significant bit (MSB) and the last bit "1" is the least significant bit (LSB). The default of the HEC calculator 14 is CRC generation and coset function execution.

The VC-4 generator 30, which receives the transmission clock and is connected to the outside through a transmission POH serial signal, indicates the start point of the cell by H4 bytes on the VC-4 POH, and simultaneously generates and inserts a pointer value for the POH. Form a VC-4 signal.

The VC-4 generator 30 is connected to the common CPU and alarm interface 28 and externally, and receives the output of the Xing HEC calculator 4, the output of the transmit clock, and the output of the B3 parity calculator 6. A transmitting POH processing unit 5 and a B3 parity calculating unit 6 which receives the output of the transmitting POH processing unit 5 are provided. Detailed description is as follows.

In the transmit POH (Paath Over Head) processing section 5, J1 has an external interface of 64 kHz and can be set to "0" by the CPU when not in use, and B3 is the BIP-8 (calculated for the previous frame). Inserts a Bit Inerleaved Parity-8 code value into the B3 byte position of the VC4 (Virtual Container 4) frame currently transmitted, and the default value of C2 is 13H, which can be changed by the CPU. Bits 1-4 of G1 are used for the path REI (Remote Error Identifier), bit 5 is used for the Remote Defect Identifier (RDI). Unused bits 6-8 are the default value "0" and are Controllable. RDI can be stopped or forcibly generated by the CPU, and REI can be stopped. H4 inserts an offset value from the H4 byte position to CH1 (cell header 1) of the ATM cell. F2 and Z3-Z5 are inserted through the external serial interface (64KHz) respectively.

The B3 parity calculator 6 calculates a bit interleaved parity-8 (BIP-8) code with even parity for the VC4 frame.

The AU-4 pointer value generator 7 receiving the transmission clock and the VC-4 signal receives the VC-4 start point J1 in the STM-1 payload to map the transmission VC-4 signal to the STM-1 frame. Pointer bytes (H1, H2) indicating the generated and applied to the STM-1 frame generation unit 31 through the Arbitray Unit Group (AUG) bus. The pointer value is fixed as "1", and the stability of pointer value, NDF (New Data Flag) used for tester of counterpart system, and function are undefined, SS bit which user assigns arbitrary value can be controlled by CPU. Do.

The STM-1 frame generator 31, which receives the transmission clock and is connected to the common CPU and the alarm interface unit 28, processes the performance / alarm information on the transmission SOH in hardware or software in real time (B1, B2, K1, K2). , F1) to be connected to an external processor, and the operation management channels E1, E2, D1 to D12, Z1, and Z2 are directly connected in series to enable communication with the outside. Framing and scrambling the data processing the information on the SOH to generate 8-bit parallel (19.440Mb / s) data, and outputs the transmission data by multiplexing the 8-bit parallel data to the received data 2: 1. The 8-bit parallel data is also output to the STM-1 frame end 34.

The STM-1 frame generator 31 is externally connected to the common CPU and alarm interface unit 28 and outputs and transmits the clock and the B2 parity calculator 9 of the AU-4 pointer value generator 7. A transmission MSOH processing section 8 which receives the output of the transmission, a B2 parity calculation section 9 which receives the output of the transmission MSOH processing section 8, a common CPU and an alarm interface section 28, and is connected to the outside. A transmission RSOH processing unit 10 for receiving the output 8 of the transmission clock and an output of the B1 parity calculation unit 12, a parallel scrambling unit 11 for receiving the output of the transmission RSOH processing unit 10 and the transmission clock; It is connected to the common CPU and the alarm interface unit 28 and has a 2: 1 multiplexer 13 for receiving and multiplexing the output and the received data of the parallel scrambling unit 11 and outputting the transmission data to the line side. Detailed description is as follows.

In the transmitting MSOH (Multiplex Section Over Head) processing section 8, B2 automatically inserts the BIP-24 value calculated for the previous frame into the B2 position of the currently transmitted STM-1 frame. K1 and K2 are inserted under the control of the CPU for ATM (Automatic Protection Switching) in the STM-1 multiple sections. Bits 6, 7, and 8 of the K2 byte are used as the multiplex section-alarm indication signal (MS-AIS) 111 and the MS-RDI 110, and have automatic detection by hardware and forced insertion removal by the CPU. . MS-RDI also has automatic insertion by hardware and disable by CPU. D4 to D12 are inserted through an external serial interface (596 Kbps), respectively. S1 is controlled through the CPU interface. Z1, Z2 and E2 are inserted through an external serial interface (64 Kbps), respectively. M1 automatically inserts the number of received B2 errors into the channel for transmitting the error status to the counterpart system as a result of receiving STM-1 multi-section BIP-24 test.

The B2 parity calculator 9 calculates a BIP-24 code with even parity for STM-1 frames excluding RSOH.

In the transmitting RSOH (Regenerator Section Over Head) processing unit 10, A1 and A2 repeatedly insert a fixed value of A1 = 28H and A2 = f6H into A1A1A1A2A2A2. The default value of C1 is "01H", which can be changed via the CPU interface, and the eighth and ninth bytes assigned to the national evi followed by C1 bytes are fixed to "AAH". B1 inserts the BIP-8 value of the previous frame into the current transmission frame. E1 is inserted from the outside through the serial interface (64 Kbps). F1 is inserted through an external CPU or external serial interface (64 Kbps). D1 to D3 are inserted through an external serial interface (192 Kbps).

The parallel scrambling unit 11 performs a scrambling function in an 8-bit parallel form at 19.44 MHz for all STM-1 data except the first 9 bytes of the STM-1 frame.

The B2 parity calculator 12 calculates a BIP-8 code with even parity on the scrambled STM-1 data.

The transmission 2: 1 multiplexer (MUX) 13 is a multiplexer that performs a remote loopback function, and outputs parallel scrambled data in a normal state and selects data transmitted from a receiver in a loopback mode.

The STM-1 frame end unit 34 receives a receive clock, receives 8-bit parallel data from the STM-1 frame generator 31, and performs 2: 1 multiplexing with 8-bit parallel received data having an SDH signal format. A section overhead (SOH) is extracted after parallel refreshing and parallel descrambling. Real-time processing (B1, B2, K1, K2, F1) of performance / alarm information on SOH is connected to external processor, and operation management channels (E1, E2, D1 to D12, Z1, Z2) are connected to the outside. Direct serial connection to enable communication.

The STM-1 frame terminator 34 is connected to a common CPU and alarm interface 28 and is a 2: 1 multiplexer 14 and a common CPU that multiplexes the output and the received data of the parallel scrambling unit 11. And a parallel refraction unit 15 connected to the alarm interface unit 28 and receiving the output of the 2: 1 multiplexer 14, and a parallel receiving the output of the parallel refraction unit 15 and a reception clock. A receiving RSOH connected to the descrambling unit 17, the common CPU and the alarm interface unit 28, and receiving an output of the parallel descrambling unit 17, a receiving clock, and an output of the B1 parity error detection unit 16; It is connected to the processing unit 18, the common CPU and the alarm interface unit 28 and external to the B2 parity error detection unit 19, the common CPU and alarm interface unit 28 that receives the output of the receiving RSOH processing unit 18 Connected and the receiving RSOH processing An output of 18 and the received clock and received MSOH processor 20 that receives the output of the B2 parity error detector 19. Detailed description is as follows.

Receive 2: 1 multiplexer (MUX) 14 is a multiplexer that performs a local loopback function, and outputs the data transmitted from the receiver in a normal state, and selects the parallel scrambled data transmitted from the transmitter in the loopback mode. At this time, clock switching is also performed.

The parallel refraction unit 15 performs the STM-1 frame synchronization function from the received 8-bit parallel data. Alarm signals detected during the reframe function include an out of frame (LOF) and a loss of frame (LOF). The OOF alarm is declared when an error occurs in four consecutive frame sync patterns, and is cleared when two consecutive frame patterns are detected. The number of occurrences of OOF is accumulated using an 8-bit counter, and an interrupt is notified to the CPU when an overflow occurs. The LOF alarm is declared when more than 24 OOFs occur, and is cleared by initializing the cumulative counter to "0" when the frame is synchronized for 3msec. The declaration and release states of the LOF are communicated to the CPU in an interrupt manner. In addition, LOS declaration and release status are input from the outside and transferred to the CPU in an interrupt method. In addition, when LOS or LOF occurs, all "1" information is automatically inserted in the forward direction, and at the same time, MS-RDI is transmitted in the reverse direction. All "1" inserts and MS-RDI auto-insertion can also be disabled by the CPU.

The B1 parity error detection unit 16 calculates a BIP-8 code with good parity for the received STM-1 frame before descrambling, compares the received B1 value with the received B1 value, and accumulates the number of errors in a 16-bit counter. . When the cumulative error number exceeds a threshold set arbitrarily by the CPU, the CPU is informed in an interrupt manner. All register values are initialized to "0" at the moment of reading. Also, the error second increases the BIES (B1 Errored Second) counter according to the presence or absence of a B1 error or OOF every 1 second.

The parallel descrambling unit 17 performs a descrambling function in 8-bit parallel form at 19.44 MHz for all STM-1 data except the first 9 bytes of the STM-1 frame. The descrambler operates in synchronization with the received STM-1 frame and uses the same polynomial as the scrambler.

The receiving RSOH processing unit 18 has a default value of C1 of " 01H " and informs the CPU in an interrupt manner when the same value is received for three consecutive frames while being different from the previous value. B1 is used to calculate the parity error, and E1 outputs through the serial interface (64 Kbps) to the outside. F1 is output via CPU or external serial interface (64Kbps). It generates an interrupt when it is 3 frames different from previous value. D1 to D3 output to the outside via an external serial interface (192 Kbps).

The B2 parity error detector 19 calculates a Bip-24 code with Even Parity for STM-1 frames excluding RSOH, compares the received B2 value, and detects an error and accumulates it in a 24-bit register. If the accumulated error number exceeds any threshold set by the CPU, the CPU is notified in an interrupt manner and the register value is initialized to "0" the moment it is read from the CPU. In addition, the error seconds are accumulated in the B2ES (B2 Errored Second) counter according to the presence or absence of a B2 parity error or OOF every 1 second, and are initialized to "0" at the time of reading from the CPU. In addition, by monitoring the transient error state of B2 bytes in 10msec units, when an excessive error state occurs, the CPU is notified by interrupt method, and all "1" is applied to the forward signal. Allow RDI to be sent automatically.

The receiving MSOH processing unit 20 automatically inserts all “1” s into payloads and D4 to D12, Z1, Z2, and E2 bytes when the MS-AIS and the transient error (Excessive-BER) occur, and its disable function Have B2 is used to calculate the parity error. K1 and K2 notifies the CPU as an interrupt when the same value is received for three consecutive frames while being different from the previous value. In addition, by monitoring the bits 6, 7, 8 of the K2 byte automatically detects the occurrence and release of the MS-AIS (111) / MS-RDI (110 consecutive data monitoring) to the CPU by interrupt method To pass. D4 to D12 output via an external serial interface (596 Kbps). S1 is different from the previous value and when the same value is received for three consecutive frames, it is sent to the CPU as an interrupt to read the received value. Z1, Z2, and E1 output through an external serial interface (64 Kbps), respectively. M1 extracts the number of transmitted B2 errors to the channel for receiving the error status from the large station as a result of the multi-section BIP-24 test and accumulates them in a 24-bit counter. If the threshold is exceeded, an interrupt is notified to the CPU.

The AU-4 pointer value analysis and processing unit 21 performs a function of interpreting the pointer bytes H1 and H2 indicating the VC4 starting point in order to extract the VC4 signal from the received STM-1 frame. At this time, the pointer synchronization state is determined by detecting all "1" (Path AIS), NDF bit, SS bit, and I / D (increment / decrement) inversion state from the received pointer value. As a result, when paths AIS and LOP are detected, the path RDI is transmitted in the reverse direction, and all "1" (RXVC4AIS) is applied to the forward signal, and then transferred to the CPU as an interrupt occurrence. When the pointer is in the normal state (Justification Evnet), it accumulates in the 16-bit register and delivers it to the CPU when the threshold is exceeded.

The VC-4 terminal 33, which receives the received clock and is connected to the outside through a transmission POH serial signal, performs a function of processing a Virtual Container-4 (VC-4) Path Over Head (POH), and the VC -4 Performs performance checks related to signal paths (B3, REI: Remote Indication Signal, Path AIS: Alarm Indication Signal, LOP: Loss of Pointer, Path RDi: Remote Defect Indication, Path Mismatch).

The VC-4 termination unit 33 is connected to a common CPU and an alarm interface unit 28 and a B3 parity error detection unit 22 and a common CPU which receive the output of the AV-4 pointer value analysis and processing unit 21. And a reception POH processing unit 23 connected to the alarm interface unit 28 and receiving an output of the AU-4 pointer value analyzing and processing unit 21, an output of a reception clock, and an output of the B3 parity error detection unit 22. Equipped. Detailed description is as follows.

The B3 parity error detection unit 22 calculates a BIP-8 code with an even parity for the VC4 frame and compares it with the received B3 value to accumulate the number of errors in a 16-bit register. When the cumulative error number exceeds an arbitrary threshold, it is transmitted to the CPU in an interrupt manner, and this state is applied to the transmission path REI to be automatically sent. In addition, the error seconds are accumulated in the B3ES (B3 Errored Second) counter according to the presence or absence of a B3 parity error or OOF every 1 second, and are initialized to "0" at the time of reading from the CPU.

In the reception POH processing section 23, J1 has an external or 1 byte CPU interface of 64 kHz. B3 may also be used to detect parity errors. The default value of C2 is " 13G ", which compares the received value with the value already specified, and delivers this state to the CPU in an interrupt manner when a three-frame consecutive mismatch is detected or an uneqipped state is detected. At the same time, the path RDI is automatically sent in the reverse direction, and all “1” is inserted into the C4 payload in the forward direction. Bits 1-4 of G1 are used for path REI and bit 5 is for RDI. A 16-bit register is used to accumulate the path REI value that occurs in every frame and is delivered to the CPU when the threshold is exceeded or when the path RDI is 10 or more times. H4 compares the received H4 value with the value found by the cell boundary identification unit and generates an interrupt to the CPU when a mismatch occurs.

The receiving ATM cell processing unit 32, which receives the receiving clock and is connected to the common CPU and the alarm interface unit 28, arranges an ATM cell mapped in the VC-4 payload, checks an error in the header unit, and processes a 1-bit error correction. Extract valid cells through. The valid cell includes a receive data (RCDATA [7: 0], a receive start (RXSOC) signal, a receive parity (RXPARITY) signal in units of bytes according to a receive cell clock (RCCLK), a receive enable signal (RXENB), which is a control signal. The RXEMPTY signal is interfaced with the ATM layer in an asynchronous manner via a first-in, first-out, where it can deliver all received valid cells or remove idle / unassigned cells. By default, descrambling of the payload of the cell is provided.

The receiving ATM cell processing unit 32 is connected to a common CPU and an alarm interface unit 28, and receives a cell boundary identification unit 24, a common CPU and an alarm that receive the output of the receiving POH processing unit 23 and a receiving clock. A cell payload descrambling unit 25, a common CPU and an alarm interface unit 28, which is connected to an interface unit 28 and receives an output of the cell boundary identification unit 24 and a reception clock, and is connected to the cell It is connected to the effective cell extracting and filtering unit 26, the common CPU and the alarm interface unit 28, which receives the output of the payload scrambling unit 25 and the receiving clock, and has a receiving cell clock (RCCLK) and a receiving enable (RXENB). ), A receive clock, an output of the valid cell extracting and filtering unit 26, and receive a receive data (RCDATA), a receive start (RXSOC) signal, a receive parity (RXPARITY) signal, a receive empty (RXEMPTY) signal To receive first-in, first-out part 27 The. Detailed description is as follows.

The cell boundary identification unit 24 achieves cell synchronization according to the following algorithm, with three states of cell synchronization achievement states of the SDH gait being "HUNT", "PRESYNC", and "SYNC". First, in the "HUNT" state, the HEC is used to find the boundary of the first valid cell from the byte-based data, and then enters the "PRESYNC" state. In the "PRESYNC" state, if there is no 8 consecutive HEC errors, it enters the "SYNC" state, otherwise it returns to the "HUNT" state again. In the " SYNC " state, the HEC error enters the " HUNT " state if it occurs in α consecutive times, otherwise it stays in the " SYNC " state. Here, the default values of δ and α are 6 and 7, respectively, and arbitrary settings can be made for values of 8 or less by the CPU. This function is enabled by the internal operating status registers, cell boundary achievement status ("HUNT", "PRESYNC", "SYNC"), HEC operation mode ("Correction Correction", "Detection mode"), and Errored cell count (single bit error cell). , Multi-bit error cell). OCD (Out of Cell Delineation) is declared when a HEC error occurs α times in the "SYNC" state, and the OCD declaration state is released immediately upon entering the "SYNC" state. If the OCD state persists for more than N msec, it declares the Loss of Cell Delineation (LCD) state, and the 'LCD alarm' outside the chip can be selected by controlling the OCD or LCD state. 'LCD alarms' cause the path RDI to propagate in the transmit direction and both the OCD and the LCD generate an interrupt. In the OCD state, the "HUNT" state and the "SYNC" state may occur intermittently, but this state is considered to be not stable and the LCD is generated the same as before. If the "SYNC" status is maintained for more than M ms after the LCD is declared, release the LCD status. The default values of N and M are 4ms and can be controlled by the CPU within the range of 0-7ms. The HEC error check in the "SYNC" state consists of two 16-bit registers, one that accumulates the number of cells where an HECD error occurred and one that counts the number of cells discarded due to an HEC error. They are disabled in the "HUNT" state and enabled only in the "SYNC" state. Each counter can be arbitrarily set by the CPU, and is sent to the CPU as an interrupt when the threshold is exceeded. The value of each register is initialized to "0" the moment the CPU reads it.

The cell payload descrambling unit 25 performs a function of inversely mixing the self-synchronized polynomial of X43 + 1 in units of bytes with respect to the cell payload information, and this function can be disabled by the CPU.

The valid cell extracting and filtering unit 26 has an error correction mode and an error detection mode in the “SYNC” state. In the error correction mode, a single error cell of the cell header part after an error correction is performed. Filtering is performed according to the cell header pattern, and two or more error cells are discarded and error cells of the cell header part are discarded in the error detection mode. In addition, the valid cell extracting and filtering unit 26 filters cells of a specific pattern under the control of the CPU based on the values of the header bytes excluding the payload among the valid cells. This function removes the inserted idle cell or cell of a specific pattern negotiated with the transmitter for cell matching function and delivers only pure serving cells. The default removes idle cells having only 1 Cell Loss Priority (CLP) bit.

The receiving cell first-in-first-out part 27 performs a temporal buffering function required for asynchronously delivering a cell delivered through VC4 to the ATM layer. That is, it provides a function of separating the operation clock of the ATM layer and the operation clock of the physical layer. The ATM layer transfers byte-based data to the ATM layer through the reception cell first-in-first-out unit 27. The receiving cell first-in-first-out part 27 has a 4-cell data capacity. When there is a receiving cell data (RCDATA [7: 0]) in units of bytes that the receiving cell first-in-first-out unit 27 sends to the ATM layer, the receiving cell RXEMPTY signal and receiving cell indicating the transfer of a valid cell. The ATM layer uses a Receive Cell Start (RXSOC) signal to indicate the location of the first byte of the ATM layer. The ATM layer detects this situation and receives the data in the first-in, first-out (CCLK) and ATM. Read using RXENB signal to indicate readability. At this time, the reception parity RXPARITY, which is an odd parity signal for data in bytes, is also transmitted. When the overflow of the reception cell first-in-first-out part 27 occurs, the reception cell first-in-first-out part 27 is automatically rested. Such a situation is transmitted to the CPU through an interrupt register.

The common CPU and alarm interface unit 28 performs a connection function such that alarm / fault monitoring, performance monitoring, operation mode control, and the like in the ASAH-P having a general-purpose CPU interface function operate in conjunction with the CPU. That is, loss of signal (LOS), loss of frame (LOP), multiplex section alarm indication signal (MS-AIS), multiplex section remote fault occurrence (MS) Multiple Section-Remote Defect Indication (RDI), Path-Alarm Indication Signal (P-AIS), Path-Remote Error Indication (P-REI), Lost Pointer (LOP: Loss) Of Pointer), Major Alarms such as Loss of Cell Delineation (LCD) and Excessive-BER (BIP Error Ratio), C2 Mismatch, Pointer Instability (Out of Cell Delineation) , B1, B2, B3, H4 / K1, K2 / F1 / S1 / C1 mismatch, Multiplex Section-Remote Error Indication (MS-REI), Errored Cell Count (ECC) Additional alarms, such as Discard Cell Count (DCC), and abnormal functions related to the operation of the FIFO. It occurs and to control the interrupt status register to "1" as a set (Set) register is interrupted, so as to identify the current alarm or release state.

The present invention made as described above is responsible for the secure transmission of data in a broadband integrated information network (B-ISDN) based on SONET / SDH (Synchronous Optical NETwork / Synchronous Digital Hierarchy), and handles errors in the data in real time, It provides a function to accumulate all statistical errors occurring on a transmission line so that a network manager can handle them, and has an effect of accommodating ATM cells in an asynchronous manner regardless of the service speed of ATM cells.

Claims (7)

In an ATM (Asynchronous Transfer Mode) physical layer subscriber access processor, a signal TXFULL indicating a write state is output to the ATM layer, and the input data TCDATA [7: 0] and a clock TCCLK in which the input data are synchronized. Scrambling of the cell payload after receiving an ATM cell from the ATM layer and receiving a transmission clock from the outside according to a transmission parity signal (TXPARITY) and a transmission control signal (TXENB, TXFSOC) which are parity signals, matching cell rates Transmitting cell processing means 29 for calculating HEC (Header Error Control) for the cell and mapping it into a VC-4 payload; Path Over Header (POH) is connected to the outside as a serial signal, and receives the output of the transmission cell processing means 29 to generate a VC-4 (Virtual Container-4) signal according to the transmission clock. VC-4 generating means (30); Receives the output of the VC-4 generating means 30 and generates the pointer bytes H1 and H2 indicating the VC-4 starting point J1 in the STM-1 payload according to the transmission clock to transmit the VC-4. Pointer generation means (7) for mapping four signals to a STM-1 (Synchronous Transfer Mode-1) frame; It is connected to the outside through a transmission MSOH (Multiplex SOH) serial signal and a transmission RSOH (Regenerator-SOH) serial signal, and receives an output of the pointer generating means 7 and receives a section overhead according to the transmission clock. Frame generation means (31) for processing the information on the header to generate parallel data, multiplexing the parallel data with the received data input from the line side, and outputting the transmission data to the line side; It is connected to the outside by the receiving MSOH (Multiplex SOH) serial signal and the receiving RSOH (Regenerator SOH) serial signal, and receives the parallel data and the receiving data from the line side to detect alarms and errors in the external receiving clock, and the section is over. Frame termination means 34 for processing information on a head (SOH: Section Over Header); A pointer analysis for extracting the VC-4 signal from the received STM-1 frame by receiving the output of the frame terminating means 34 and interpreting the pointer bytes H1 and H2 indicating the VC-4 starting point according to the received clock; Processing means 21; Path Over Header (POH) is connected to the outside as a serial signal, and receives the output of the pointer analysis and processing means 21 to process error detection and information on path overhead according to the received clock. VC-1 termination means 33; Receives an RXENB signal indicating an operation clock (RCCLK) of the ATM layer and a data read state of the ATM layer, receives an output of the VC-4 terminating means 33, and receives a cell according to the received clock. After identifying the boundary, descrambling of the cell payload and valid cells are extracted, and then filtered according to the control of the central controller to output data (RCDATA [7: 9]), a received parity signal (RXPARITY) which is a parity signal, Receiving cell processing means (32) for outputting a reception empty (RXEMPTY) signal informing of the delivery of an effective cell and a reception cell start (RXSOC) signal indicating a start position of a cell to the ATM layer; And connection means (28) for connecting said respective means (21,29 to 34) and an external central processing unit (CPU). The transmission cell processing means 29 according to claim 1, wherein the transmission cell processing means 29 outputs a signal TXFULL indicating the write state to the ATM layer, and synchronizes the input data TCDATA [7: 0] with the input data. After receiving the ATM cell from the ATM layer according to the clock TCCLK and the transmission control signals TXENB, TXFSOC and TXPARITY, the clock TCCLK synchronized with the input data is transferred to the transmission clock and the input data is converted into the transmission clock. Cell first-in, first-out means (1) for buffering in time and generating an interrupt to the external central processing unit (CPU) when overflow occurs and being controlled by the external central processing unit; Receiving the output of the cell first-in, first-out means and the transmission clock, the cell transmission rate in the ATM layer and the cell transmission rate in the SDH (Synchronous Digital Hierachy) transmission path are matched, and the external central processing unit ( Transmission rate matching means (2) for changing a cell header and a payload different from the cell transmission rate matching under control of the CPU; Mixing means (3) receiving the output of the transmission rate matching means (2) and the transmission clock to mix payload information of a cell according to a self-synchronizing generation polynomial, and to be controlled by the external central processing unit (CPU) ; And an HEC checking means (4) which receives the output of the mixing means (3) and the transmission clock and performs a cyclic redundancy check (CRC) to check the HEC and is controlled by the external central processing unit (4). ATM physical layer subscriber access processor comprising a. The apparatus of claim 1, wherein the VC-4 generating means (30) inputs and outputs data to and from the outside through the transmission path overhead (POH) serial signal, and outputs the HEC check means (4). Path overhead processing means (5) receiving a bit interleaved parity (BIP-8) code calculated for a previous frame, processing information on path overhead according to the transmission clock, and being controlled by the external central processing unit (5) ; And a parity calculating means (6) which receives the output of the path overhead processing means (5), calculates the BIP-8 code, and outputs it to the path overhead processing means (5). Layer subscriber access handler. 2. The frame generating means (31) according to claim 1, wherein the frame generating means (31) inputs and outputs data to and from the outside through the transmission MSOH (Multiplex SOH) serial signal, and the BIP calculated for the output of the pointer generating means (7) and the previous frame. Receives a -24 code, processes information on a transmission multi-section overhead (MSOH) according to the transmission clock, and performs automatic protection switching (APS) on a frame multi-section according to the control of the external central processing unit. Multi-section overhead processing means 8; First parity calculating means (9) for receiving the output of the multi-section overhead processing means (8), calculating the BIP-24 code, and outputting the BIP-24 code to the multi-section overhead processing means (8); Data is inputted and outputted from the outside through the transmission RSOH (Regenerator SOH) serial signal, and the output of the multi-section overhead processing means 8 and the BIP-8 code calculated for the previous frame are received and transmitted according to the transmission clock. Reproducing section overhead processing means (10) for processing information on a reproducing section overhead (RSOH) and being controlled by the external central processing unit; Mixing means (11) for receiving an output of said reproduction section overhead processing means (10) and mixing according to said transmission clock; Second parity calculating means (12) for receiving the output of the mixing means (11), calculating the BIP-8 code, and outputting the BIP-8 code to the reproduction section overhead processing means (10); And multiplexing means (13) for receiving the output of the mixing means (11) and the received data from the line side and multiplexing under the control of the external central processing unit, and then outputting the transmission data to the line side. ATM physical layer subscriber access handler. 2. The multiplexing means according to claim 1, wherein the frame terminating means (34) is configured to multiplex data and switch clocks under the control of the external central processing unit by receiving the output of the mixing means and the received data from the line side. (14); Frame reproducing means (15) for receiving an output of the multiplexing means (14) for detecting an error and reproducing a frame under the control of the external central processing unit; First parity error detection means (16) for receiving an output of said frame reproducing means (15), calculating a BIP-8 code to detect an error, and then processing it under the control of said external central processing unit; Demixing means (17) for receiving the output of the frame reproducing means (15) and performing demixing in accordance with the received clock; Data is inputted and outputted to the outside via the received RSOH (Regenerator SOH) serial signal, and the output of the demixing means 17 and the first parity error detecting means 16 is received and over the received reproduction section according to the received clock. A reproduction section overhead processing means (18) for processing information on the head and being controlled by the external central processing unit; Second parity error detection means (19) for receiving an output of said reproduction section overhead processing means (18), calculating a BIP-24 code to detect an error, and then processing it under control of said external central processing unit; And input / output data to and from the outside through the received multiplex SOH (serial multiplex) serial signal, and receive the outputs of the reproduction interval overhead processing means 18 and the second parity error detection means according to the received clock. And multi-section overhead processing means (20) for processing information on overhead (MSOH) and controlled by the external central processing unit. The apparatus of claim 1, wherein the VC-4 terminating means (33) receives an output of the pointer analysis and processing means (21), calculates a BIP-8 code, detects an error, and detects the external central processing unit. Parity error detection means (22) under the control of; And input and output data to and from the outside through the path over header (POH) serial signal, and receive the outputs of the pointer analysis and processing means 21 and the parity error detection means 22 to the transmission clock. And path overhead processing means (23) for processing information on path overhead and under control of said external central processing unit. The cell of claim 1, wherein the receiving cell processing unit 32 receives an output of the path overhead processing unit 23 to synchronize a cell according to the reception clock and is controlled by the external central processing unit. Boundary identification means 24; Demixing means for receiving the output of the cell boundary identifying means 24 and the received clock to demix the payload information of the cell according to a self-synchronizing polynomial, and being controlled by the external central processing unit (CPU) ( 25); Cell extraction and filtering means (26) for receiving an output of the demixing means (25) and a receiving clock, discarding the error cell to extract a valid cell, and then filtering the outside to remove the non-service cell under the control of the central processing unit (26). ; And receiving the output of the cell extracting and filtering means 26, outputting the RXEMPTY signal and the RXSOC signal to the ATM layer, and then enabling the operation clock RCCLK and the reception enable. Receive a (RXENB) signal from the ATM layer and buffer the time while outputting the output data (RCDATA [7: 0]) and a received parity signal to the ATM layer, and buffering the operation clock (RCCLK) ATM physical layer subscriber, comprising: first-in, first-out means (27) for switching to a received clock and generating an interrupt to the external central processing unit (CPU) when an overflow occurs and being controlled by the external central processing unit. Access handler.