KR970001350B1 - Nand gate & method of manufacturing the same - Google Patents

Abstract

The present invention relates to a NAND gate having a first gate and a second gate on a portion of a substrate between a source/drain to form a logic in a small area, and two or three input terminals, and a method of making the NAND gate. This method can reduce the size of the NAND gate occupied in the semiconductor device's interior and signal transmission delay, and simplifies the circuit layout. The inventive NAND gate with two input terminals and one output terminal includes a source/drain on a silicon substrate; a first gate formed on a certain region of the substrate between the source/drain and receiving a first input signal; a conductive spacer formed on the first gate's one sidewall and covering the rest of the substrate between the source/drain; and a MOS FET with two gates to which a second input

Description

NAND gate using one MOSFET and manufacturing method

1 is a circuit diagram showing an example of a conventional NAND gate.

2 is a circuit diagram showing a NAND gate of the present invention.

FIG. 3A is a sectional view showing a NAND gate manufactured by the first embodiment of the present invention. FIG.

3B is an equivalent circuit diagram of a NAND gate manufactured by the first embodiment of the present invention.

4A to 4F are cross-sectional views showing steps for manufacturing a NAND gate of a first embodiment of the present invention.

FIG. 5A is a sectional view showing a NAND gate manufactured by the second embodiment of the present invention. FIG.

5B is an equivalent circuit diagram of a NAND gate manufactured by the second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1, 7: gate 2, 45: drain

3, 46: source 4: conductive layer spacer

5, 6: channel 8, 10: silicon substrate

41 gate 42, 47 oxide film

43: conductive layers 44, 44A, 44B: conductive layer spacer

48, 48A, 48B: second gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND gate of a semiconductor device and a method of manufacturing the same. In particular, in order to configure logic in a narrow area, a second layer is stacked with a first gate and a floating gate on a substrate between one source and a drain. A NAND gate having a gate or two or three input terminals and a method of manufacturing the same.

A large amount of NAND gates are used to implement the logic of the semiconductor device, and these NAND gates are implemented with three or more general MOS transistors, which not only increases the area occupied by the NAND gates but also pull-ups. ), There is a problem in that a time delay caused by using a pull-down transistor and a circuit layout are combined.

Accordingly, an object of the present invention is to provide a NAND gate implemented by forming two or more gates on a substrate between one source and a drain to improve the degree of integration, and a method of manufacturing the same.

In order to achieve the above object, the present invention provides a NAND gate having two input terminals and one output terminal of a semiconductor device, the source and drain formed on a silicon substrate and a portion formed on an upper portion of the silicon substrate between the source and the drain. A first gate to which a first input signal is applied, the first gate is formed on one sidewall, and a conductive layer spacer covering the remaining portion of the upper portion of the silicon substrate existing between the source and the drain, and an upper portion of the conductive layer spacer. A MOS transistor having two gates including a surface and a second gate to which a second input signal is applied is overlapped with a predetermined upper surface of the first gate.

Hereinafter, a structure and a manufacturing method of a NAND gate will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an example of a conventional NAND gate. The transistors M11 and M12 are connected in parallel while receiving two input signals Vin1 and Vin2 as gates to supply charges to the output terminal Vout, and two as gates. It consists of transistors M13 and M14 which are connected in series to receive the input signals Vin1 and Vin2, and discharge the charge at the output terminal Vout.

When a signal having logic high is input to the input terminals Vin1 and Vin2 at the same time, transistors M11 and M12 are turned off, and transistors M13 and M14 are turned on to output Vout to a logic low state. One of the two input signals has a logic low state and one of the transistors M11 and M12 is turned on, and one of the transistors M13 and M14 is turned off so that the charge at the output terminal Vout is not discharged and is supplied by the supplied charge. It has a logic high state.

When the NAND gate is configured as shown in FIG. 1, a plurality of transistors are required to implement a single NAND gate, and accordingly, a signal propagation time is delayed due to an increase in area, a pull-up, and a pull-down transistor. Problems, such as a complicated layout of circuit layout, and the like.

Accordingly, in the present invention, in order to eliminate the above problems, the NAND gate is formed of one MOS transistor having two or more gates.

2 is a circuit diagram showing a NAND gate of the present invention, which is constructed by using one MOS transistor having two gates and a resistance component.

Since the NAND gate of FIG. 2 uses one NMOS transistor M20 having two input signals Vin1 and Vin2, gain is large in area of one NAND gate, and does not use a pull-up transistor and pulls down Since only one transistor is used, the delay of the signal propagation time can be reduced.

3A and 3B are cross sectional views showing the first embodiment of the present invention manufactured on a silicon substrate, and an equivalent circuit diagram thereof.

In operation, when a logic high signal is applied to the two gates 1 and 7, a channel 5 and 6 is formed between the drain 2 and the source 3 so that the output terminal Vout has a logic low state. When a logic low is applied to any one of the two gates 1 and 7, the corresponding channel 5 or 6 is lost and the output terminal Vout is maintained at the logic high state.

As shown in FIG. 3A, the gate 7 forms a channel by using capacitive coupling. When a voltage is applied to the gate 7, the gate 7 and the conductive layer spacer ( 4) and the voltage is induced in the silicon substrate 8 according to the oxide thickness ratio between the silicon substrates 8, and thus the channel 6 is formed.

4A to 4F are sectional views showing the steps of manufacturing the NAND gate of the first embodiment of the present invention.

4A illustrates that after forming the first gate 41 on the silicon substrate 100, an oxidation process is performed to form an oxide film 42 along the upper surface thereof, and then to the conductive layer 43, for example. Polysilicon (Polysilicon) is a cross-sectional view of the deposition.

FIG. 4B is a cross-sectional view of one portion of the conductive layer 43 being etched around the first gate 41 after the process of FIG. 4A.

4C is a cross-sectional view of the conductive layer spacer 44 used as a floating gate on the sidewall of the gate 41 by etching back one conductive layer 43 that is not etched after the process of FIG. 4B. to be.

4D illustrates that the source 46 and the drain 45 are formed by injecting N-type impurities into the substrate using the first gate 41 and the conductive layer spacer 44 as a self-align mask after the process of FIG. 4C. The cross section is formed.

4E is a cross-sectional view of depositing a thin oxide film 47 along the upper surface after the process of FIG. 4D and depositing a conductive layer 48, for example, a polysilicon layer thereon.

FIG. 4f shows a second gate 41 overlapping the conductive layer spacer 44 by etching one side of the conductive layer 48 after the process of FIG. 4e to form the first gate and the first gate and drain between one source and a drain. A cross-sectional view of a NAND gate manufactured by fabricating a MOS transistor having two gates.

An N-well (not shown) may be formed on the silicon substrate 100 of FIGS. 4A through 4F, and the source 46 and the drain 45 may be manufactured using a P + active layer to manufacture a PMOS NAND gate.

5A and 5B are cross-sectional views and equivalent circuit diagrams of a second embodiment of the present invention fabricated on a silicon substrate, wherein three gates are provided between one source and drain using two conductive layer spacers. This is to form a NAND gate structure.

As in the processes of FIGS. 4A to 4F, first, a first gate 41 is formed on the silicon substrate 100, an oxide film 42 is formed on the upper surface thereof, and a conductive layer is coated to etch it. After the conductive layer spacers 44A and 44B are formed on both sides of the first gate 41 by the process, a thin oxide film 47 is further deposited on top of the first gate 41, and then the conductive layer 48 is applied. Subsequently, the second gates 48A and 48B overlapping the conductive layer spacers 44A and 44B are separated into two by etching a portion of the center portion of the conductive layer 48 around the first gate 41. By forming N, three gates are provided on the substrate between one source and a drain to complete a NAND gate structure having three input terminals.

5A to 5B, the NAND gate including the PMOS transistor or the NMOS transistor can be selectively manufactured by making the active layer an N + type or a P + type.

As described in the above-described embodiments of the present invention, when a NAND gate is formed by forming an upper portion of a substrate between a single source and a drain having multiple gates, the NAND gate is implemented as compared with the conventional NAND gate using a plurality of MOSFETs. Not only can reduce the area occupied within the semiconductor device, but also reduce the propagation delay time of the signal during operation and simplify the layout of the circuit.

Claims (6)

A NAND gate having two input terminals and one output terminal of a semiconductor device, comprising: a first source and a drain formed on a silicon substrate, and a first input signal formed on a portion of an upper portion of the silicon substrate between the source and the drain and to which a first input signal is applied; A conductive layer spacer formed on one sidewall of the gate and covering the remaining portion of the upper portion of the silicon substrate between the source and the drain; an upper surface of the conductive layer spacer and a predetermined upper portion of the first gate; A NAND gate using a MOSFET, wherein the NMOS gate comprises one MOS transistor having two gates each including a second gate to which the second input signal is applied. The NAND gate of claim 1, wherein the conductive layer spacer is floating while being insulated from the first and second gates. In manufacturing a NAND gate having two input terminals and one output terminal of a semiconductor device, after forming a first gate on a silicon substrate, an oxidation process is performed to form an oxide film on the upper surface thereof, and then conductive on the upper portion thereof. Depositing a layer, etching one portion of the conductive layer in one direction about the first gate, and etching back the remaining conductive layer to a sidewall of the first gate as a floating gate. Forming a conductive layer spacer to be used; implanting impurities into the silicon substrate using the first gate and the conductive layer spacer as a mask; forming a source and a drain; depositing a thin oxide film over the entire surface; Depositing a conductive layer on the upper portion, and etching a portion of the conductive layer to form a second gate overlapping the conductive layer spacer NAND gate method using a single MOSFET which comprises a. A NAND gate having a semiconductor device, three input terminals, and one output terminal, comprising: a source and a drain formed on a silicon substrate, and a first input signal formed on a portion of an upper portion of the silicon substrate between the source and the drain and to which a first input signal is applied; Two independent conductive layer spacers formed on both sidewalls of the first gate and covering the remaining portion of the upper portion of the silicon substrate existing between the source and the drain, and overlapping the two conductive layer spacers, respectively. And second and third gates to which the third input signal is applied, and thus three gates are configured in one MOS transistor. The NAND gate of claim 4, wherein the conductive layer spacer is floated in an insulated state from the first, second, and third gates. In manufacturing a NAND gate having three input terminals and one input terminal of a semiconductor device, after forming a first gate on a silicon substrate, an oxidation process is performed to form an oxide film on the upper surface thereof, and then to conduct the upper portion thereof. Depositing a layer, etching the conductive layer to form a conductive layer spacer used for floating gates on both sides of the first gate, and using the first gate and the conductive layer spacer as a mask to form impurities as a substrate. Implanting to form a source and a drain, depositing an oxide film over the entire surface, depositing a conductive layer thereon, and cutting a portion of the conductive layer to overlap each of the conductive layer spacers. Forming a gate so that three gates are provided in one MOS transistor. The NAND gate method using a single MOSFET.