KR960043623A - Data and Clock Automatic Regeneration Circuit of Optical Receiver - Google Patents

Data and Clock Automatic Regeneration Circuit of Optical Receiver Download PDF

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Publication number
KR960043623A
KR960043623A KR1019960043421A KR19960043421A KR960043623A KR 960043623 A KR960043623 A KR 960043623A KR 1019960043421 A KR1019960043421 A KR 1019960043421A KR 19960043421 A KR19960043421 A KR 19960043421A KR 960043623 A KR960043623 A KR 960043623A
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KR
South Korea
Prior art keywords
data
clock
circuit
optical receiver
analyze
Prior art date
Application number
KR1019960043421A
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Korean (ko)
Inventor
공비호
Original Assignee
공비호
주식회사 아이티
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 공비호, 주식회사 아이티 filed Critical 공비호
Priority to KR1019960043421A priority Critical patent/KR960043623A/en
Publication of KR960043623A publication Critical patent/KR960043623A/en

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Abstract

본 발명은 사용하는 데이타의 주파수 성분, 즉 클럭이 고정되어 있는 기존의 광수신기 모듈과는 다르게, 광섬유를 통하여 전송되어진 데이타의 클럭 성분을 검출하고, 이 정보를 마이크로 프로세서에서 분석하여 위상 동기 루프의 파라메터를 변환, 정상적인 데이타와 클럭을 재생하는 기능을 가진 광수신기에 관한 것으로 광전 변환회로(10)에서 광신호로부터 전기신호로 변환한 후, 데이타 주파수 검출회로(60)를 통하여 클럭 주파수 성분을 검출하고, 이 검출된 주파수 값을 마이크로 프로세서 제어회로(40)에 인가시켜 검출된 주파수 값을 분석한 후 데이타 및 클럭 재생회로(20)안에 있는 위상동기 루프의 파라메터 값으로 변환시키게 구성시킴으로써 광신호를 변환시킨 전기신호를 정상적인 데이타 및 클럭으로 재생하게 된다.The present invention detects a frequency component of data to be used, that is, a clock component of data transmitted through an optical fiber, unlike a conventional optical receiver module having a fixed clock, and analyzes this information in a microprocessor to analyze a phase locked loop. The present invention relates to an optical receiver having a function of converting a parameter and reproducing a normal data and a clock. And applying the detected frequency value to the microprocessor control circuit 40 to analyze the detected frequency value and converting the detected frequency value into a parameter of the phase-locked loop in the data and clock reproduction circuit 20. The converted electrical signal is reproduced with normal data and clock.

Description

광수신기의 데이타 및 클럭 자동 재생 회로Data and Clock Automatic Regeneration Circuit of Optical Receiver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 구성도.2 is a block diagram of the present invention.

Claims (1)

광섬유를 통해 전송되어진 광신호를 광전변환회로에서 전기신호로 변환시키고 이를 데이타 및 클럭 재생 회로에서 데이타 및 클럭으로 변환시키는 광수신기 모듈에 있어서, 광전변환회로에서 변환된 데이타 성분에서 광신호가 갖고 있는 주파수 성분을 검출하는 데이타 주파수 검출회로와, 데이타 주파수 검출회로에서 검출된 주파수 성분값을 분석하여 정상적인 데이타와 클럭을 재생할 수 있도록 데이타 및 클럭 재생회로의 위상동기 루프의 파라메터를 자동으로 변경시키는 마이크로 프로세서 제어회로를 구비시킨 것을 특징으로 하는 광수신기의 데이타 및 클럭 자동재생회로.An optical receiver module that converts an optical signal transmitted through an optical fiber into an electrical signal in a photoelectric conversion circuit and converts it into a data and a clock in a data and clock reproduction circuit, wherein the frequency of the optical signal in the data component converted in the photoelectric conversion circuit Microprocessor control that automatically changes the parameters of the phase-locked loop of the data and clock regeneration circuit to analyze the data frequency detection circuit for detecting components and the frequency component values detected by the data frequency detection circuit to reproduce normal data and clocks. A data and clock automatic reproduction circuit of an optical receiver, comprising a circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960043421A 1996-09-25 1996-09-25 Data and Clock Automatic Regeneration Circuit of Optical Receiver KR960043623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960043421A KR960043623A (en) 1996-09-25 1996-09-25 Data and Clock Automatic Regeneration Circuit of Optical Receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960043421A KR960043623A (en) 1996-09-25 1996-09-25 Data and Clock Automatic Regeneration Circuit of Optical Receiver

Publications (1)

Publication Number Publication Date
KR960043623A true KR960043623A (en) 1996-12-23

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ID=66325188

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960043421A KR960043623A (en) 1996-09-25 1996-09-25 Data and Clock Automatic Regeneration Circuit of Optical Receiver

Country Status (1)

Country Link
KR (1) KR960043623A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001080025A1 (en) * 2000-04-15 2001-10-25 Opticis Co., Ltd. Universal serial bus connecting apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001080025A1 (en) * 2000-04-15 2001-10-25 Opticis Co., Ltd. Universal serial bus connecting apparatus

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