KR840005635A - Lock Detection Method of PLL for Clock Generation in Digital Modulated Signal Reading Apparatus - Google Patents

Lock Detection Method of PLL for Clock Generation in Digital Modulated Signal Reading Apparatus Download PDF

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Publication number
KR840005635A
KR840005635A KR1019830002839A KR830002839A KR840005635A KR 840005635 A KR840005635 A KR 840005635A KR 1019830002839 A KR1019830002839 A KR 1019830002839A KR 830002839 A KR830002839 A KR 830002839A KR 840005635 A KR840005635 A KR 840005635A
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KR
South Korea
Prior art keywords
pll
signal reading
detection method
clock generation
modulated signal
Prior art date
Application number
KR1019830002839A
Other languages
Korean (ko)
Other versions
KR860001260B1 (en
Inventor
다다히로(외 1) 야마구찌
Original Assignee
마쓰모도 세이야
파이오니아 가부시기 가이샤
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Application filed by 마쓰모도 세이야, 파이오니아 가부시기 가이샤 filed Critical 마쓰모도 세이야
Publication of KR840005635A publication Critical patent/KR840005635A/en
Application granted granted Critical
Publication of KR860001260B1 publication Critical patent/KR860001260B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

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  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dc Digital Transmission (AREA)

Abstract

내용 없음No content

Description

디지탈 변조신호 판독장치에 있어서의 클록발생용 PLL의 록 검출방식Lock Detection Method of PLL for Clock Generation in Digital Modulated Signal Reading Apparatus

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 제1도에 있어서의 입력신호의 포오매트를 나타낸 파형도.FIG. 2 is a waveform diagram showing the pore mat of the input signal in FIG.

제3도는 본 발명의 실시예 블록도.3 is an embodiment block diagram of the present invention.

제4도는 제3도에 있어서의 프레임 동기제어회로(11)의 구체예를 표시한 블록도.4 is a block diagram showing a specific example of the frame synchronization control circuit 11 in FIG.

Claims (1)

소정의 프레임 동기신호를 포함하고 또한 셀프클록이 가능한 변조방식에 의해 기록 또는 전송된 디지탈 변조신호를 판독하는 디지탈 변조신호의 판독장치에 있어서 재생클록을 발생시키기 위한 PLL이 록상태로 된 것을 검출하는 방식으로서, 상기 재생클록에 의해서 상기 소정의 프레임 동기신호를 검출하여 각 프레임의 최초의 데이터의 도래를 검지하여 상기 최초의 데이터의 도래에 동기하여 복호화가 행해지도록 제어어하는 프레임 동기 제어수단이 헌팅동작을 정지한 것을 가지고 상기 PLL이 록 한 것이라고 판단하는 것을 특징으로 하는 디지탈 변조신호 판독장치에 있어서의 클록 발생용 PLL의 록 검출방식.A digital modulation signal reading device that reads a digital modulation signal recorded or transmitted by a modulation method capable of self-clocking and including a predetermined frame synchronization signal, for detecting that a PLL for generating a reproduction clock is in a locked state. As a scheme, the frame synchronization control means for detecting the predetermined frame synchronization signal by the reproduction clock to detect the arrival of the first data of each frame and to perform decoding in synchronization with the arrival of the first data is hunted. A lock detection method for a PLL for clock generation in a digital modulated signal reading device, characterized in that the PLL is determined to be locked by stopping the operation. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019830002839A 1982-07-27 1983-06-23 Phase-locked loop detecting circuit KR860001260B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57131008A JPS5921156A (en) 1982-07-27 1982-07-27 Lock detecting system of clock generating pll of digitally modulated signal reader
JP131008 1982-07-27

Publications (2)

Publication Number Publication Date
KR840005635A true KR840005635A (en) 1984-11-14
KR860001260B1 KR860001260B1 (en) 1986-09-01

Family

ID=15047806

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830002839A KR860001260B1 (en) 1982-07-27 1983-06-23 Phase-locked loop detecting circuit

Country Status (3)

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US (1) US4535306A (en)
JP (1) JPS5921156A (en)
KR (1) KR860001260B1 (en)

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Publication number Priority date Publication date Assignee Title
US5182761A (en) * 1991-01-31 1993-01-26 Motorola, Inc. Data transmission system receiver having phase-independent bandwidth control
US5396109A (en) * 1991-09-26 1995-03-07 Olympus Optical Co., Ltd. Bit clock regenerating circuit and data regenerating method
JPH11284674A (en) * 1998-03-30 1999-10-15 Nec Shizuoka Ltd Selective radio call receiver and synchronism control method therefor
JP2000278344A (en) * 1999-03-25 2000-10-06 Sanyo Electric Co Ltd Pseodo lock detection system
US6891441B2 (en) * 2002-11-15 2005-05-10 Zoran Corporation Edge synchronized phase-locked loop circuit
US7272201B2 (en) * 2003-08-20 2007-09-18 Schweitzer Engineering Laboratories, Inc. System for synchronous sampling and time-of-day clocking using an encoded time signal
US7398411B2 (en) * 2005-05-12 2008-07-08 Schweitzer Engineering Laboratories, Inc. Self-calibrating time code generator
BRPI1013707A2 (en) * 2009-04-03 2019-09-24 Schweitzer Eng Laboratoires Inc time signal drift correction methods for an intelligent electronic device to determine in weighted average time signal, intelligent electronic device (ied), and method for determining and distributing a weighted average time signal in a weighted distribution system. electric power.
US8351433B2 (en) * 2009-09-18 2013-01-08 Schweitzer Engineering Laboratories Inc Intelligent electronic device with segregated real-time ethernet
US8867345B2 (en) * 2009-09-18 2014-10-21 Schweitzer Engineering Laboratories, Inc. Intelligent electronic device with segregated real-time ethernet
US8812256B2 (en) 2011-01-12 2014-08-19 Schweitzer Engineering Laboratories, Inc. System and apparatus for measuring the accuracy of a backup time source
US9324122B2 (en) 2012-10-19 2016-04-26 Schweitzer Engineering Laboratories, Inc. Voting scheme for time alignment
US9300591B2 (en) 2013-01-28 2016-03-29 Schweitzer Engineering Laboratories, Inc. Network device
US9065763B2 (en) 2013-03-15 2015-06-23 Schweitzer Engineering Laboratories, Inc. Transmission of data over a low-bandwidth communication channel
US9620955B2 (en) 2013-03-15 2017-04-11 Schweitzer Engineering Laboratories, Inc. Systems and methods for communicating data state change information between devices in an electrical power system
US9270109B2 (en) 2013-03-15 2016-02-23 Schweitzer Engineering Laboratories, Inc. Exchange of messages between devices in an electrical power system
US9967135B2 (en) 2016-03-29 2018-05-08 Schweitzer Engineering Laboratories, Inc. Communication link monitoring and failover
US10819727B2 (en) 2018-10-15 2020-10-27 Schweitzer Engineering Laboratories, Inc. Detecting and deterring network attacks
US11522358B2 (en) 2020-05-18 2022-12-06 Schweitzer Engineering Laboratories, Inc. Isolation of protective functions in electrical power systems
US11862958B2 (en) 2021-10-04 2024-01-02 Schweitzer Engineering Laboratories, Inc. Isolation of protection functions in electrical power systems during startup

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3525945A (en) * 1968-08-14 1970-08-25 Communications Satellite Corp System for reconstituting a carrier reference signal using a switchable phase lock loop
JPS5625847A (en) * 1979-08-09 1981-03-12 Oki Electric Ind Co Ltd Change-over system of clock distribution system
US4473801A (en) * 1979-12-17 1984-09-25 Robert Maurer Demodulator circuit with phase control loop

Also Published As

Publication number Publication date
JPS5921156A (en) 1984-02-03
KR860001260B1 (en) 1986-09-01
US4535306A (en) 1985-08-13

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