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Application filed by Lite On Comm Corp, Lite On Comm IncfiledCriticalLite On Comm Corp
Priority to TW84108413ApriorityCriticalpatent/TW267277B/en
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Publication of TW267277BpublicationCriticalpatent/TW267277B/en
Synchronisation In Digital Transmission Systems
(AREA)
Abstract
A digital phase-locked loop that comprises zero phase start-up circuit, phase error detecting circuit, adaptive error filtering circuit, receiving clock adjusting circuit and clock generating circuit features that in zero start-up circuit by detecting transmission data level a set of clock is generated rapidly to lock transmission data phase, and by phase error between detected transmission data phase of phase error detecting circuit and receiving clock phase the phase error signal is filtered through adaptive error filtering circuit and converted to error adjusting signal. The receiving clock adjusting circuit adjusts receiving clock phase to make receiving clock phase synchronous with transmission data phase based on the error adjusting signal.