KR960043099A - Semiconductor Device Isolation Method - Google Patents

Semiconductor Device Isolation Method Download PDF

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KR960043099A
KR960043099A KR1019950012738A KR19950012738A KR960043099A KR 960043099 A KR960043099 A KR 960043099A KR 1019950012738 A KR1019950012738 A KR 1019950012738A KR 19950012738 A KR19950012738 A KR 19950012738A KR 960043099 A KR960043099 A KR 960043099A
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South Korea
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device isolation
oxide film
isolation region
etching
film
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KR1019950012738A
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Korean (ko)
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KR0149229B1 (en
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정연국
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문정환
Lg 반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

본 발명은 두꺼운 산화막을 이용하여 단일 소자간을 전기적으로 격리시키는 반도체 소자 격리방법에 관한 것으로, 특히 필드산화막의 단차를 줄이므로써 필드산화막 형성 후 이후 공정에서 막 증착시에 막 끊김 및 막 증착후 식각불량을 방지를 위해, 1) 실리콘기판상에 패드산화막(SiO2)과 질화막(Si3N4)층을 순차로 형성하는 단계와, 2) 소자격리영역의 질화막을 제거하는 단계와, 3) 질화막층 및 실리콘기판에 대하여 선택적으로 소자격리영역의 패드산화막을 습식각으로 등방성식각 제거하되, 패드산화막 두께를 초과하여 식각하여 소정길이만큼 측면식각하는 단계와, 4) 소자격리영역의 실리콘기판을 습식각으로 등방성식각하는 단계와, 5) 소자격리영역에 필드산화막을 형성하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device isolation method for electrically isolating a single device by using a thick oxide film. In particular, after the field oxide film is formed by reducing the step difference of the field oxide film, the film is broken and the film is deposited during the film deposition in the subsequent process. In order to prevent etch defects, 1) sequentially forming a pad oxide film (SiO 2 ) and a nitride film (Si 3 N 4 ) layer on a silicon substrate, 2) removing the nitride film of the device isolation region, 3 4) isotropically removing the pad oxide film of the device isolation region by wet etching selectively with respect to the nitride film layer and the silicon substrate, and etching side surface by a predetermined length by etching beyond the thickness of the pad oxide film, and 4) silicon substrate of the device isolation region. Isotropically etching by wet etching, and 5) forming a field oxide film in the device isolation region.

Description

반도체 소자 격리방법Semiconductor Device Isolation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 반도체 소자 격리방법을 설명하기 위해 도시한 반도체 소자의 일부 단면도.2 is a partial cross-sectional view of the semiconductor device shown for explaining the semiconductor device isolation method of the present invention.

Claims (4)

소자격리영역에 두꺼운 산화막을 형성하여 단위 소자간 전기적으로 격리시키는 반도체 소자 격리방법에 있어서, 1) 실리콘기판상에 패드산화막(SiO2)과 질화막(Si3N4)층을 순차로 형성하는 단계와, 2) 상기 소자격리영역의 질화막을 제거하는 단계와, 3) 상기 질화막층 및 실리콘기판에 대하여 선택적으로 상기 소자격리영역의 패드산화막을 습식각으로 등방성식각 제거하되, 패드산화막 두께를 초과하여 식각하여 소정길이만큼 측면식각하는 단계와, 4) 상기 소자격리영역의실리콘기판을 습식각으로 등방성식각하는 단계와, 5) 상기 소자격리영역에 필드산화막을 형성하는 단계를 포함하여 이루어진 반도체 소자 격리방법.In the semiconductor device isolation method for forming a thick oxide film in the device isolation region to electrically isolate between the unit devices, 1) forming a pad oxide film (SiO 2 ) and a nitride film (Si 3 N 4 ) in sequence on the silicon substrate 2) removing the nitride film of the device isolation region; and 3) selectively removing the pad oxide film of the device isolation region by wet etching with respect to the nitride layer and the silicon substrate. Etching to the side by a predetermined length by etching, 4) isotropically etching the silicon substrate in the device isolation region by wet etching, and 5) forming a field oxide film in the device isolation region. Way. 제1항에 있어서, 상기 3)단계에서 패드산화막(SiO2)의 측면식각 길이는, 패드산화막 두께의 약 5 배 내지 6배까지 식각하는 것을 특징으로 하는 반도체 소자 격리방법.The method of claim 1, wherein the side etching length of the pad oxide layer (SiO 2 ) is etched by about 5 to 6 times the thickness of the pad oxide layer. 제1항 또는 제2항에 있어서, 상기 1)단계에서 상기 패드산화막(SiO2)은 열산화로, 상기 질화막(Si3N4)층은 저압화학기상증착(LPCVD)법으로 형성하는 것이 특징인 반도체 소자 격리방법.The method of claim 1 or 2, wherein in step 1), the pad oxide film (SiO 2 ) is formed by thermal oxidation, and the nitride film (Si 3 N 4 ) layer is formed by low pressure chemical vapor deposition (LPCVD) method. Semiconductor device isolation method. 제1항 또는 제2항에 있어서, 상기 2)단계에서 상기 소자격리영역의 질화막의 제거는 사진감광공정(PhotoLithography)으로 소자격리영역을 정의한 후 포토레지스트를 식각마스크로 하여 건식각(Dry Etch)으로 제거하고, 상기 포토레지스트는 상기 4)단계 후에 제거하는 것이 특징인 반도체 소자 격리방법.3. The method of claim 1, wherein the nitride film of the device isolation region is removed in step 2) by defining a device isolation region by a photolithography process, and then using a photoresist as an etching mask. Removing the photoresist and removing the photoresist after step 4). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950012738A 1995-05-22 1995-05-22 Method of semiconductor device isolation KR0149229B1 (en)

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