KR960043030A - Method of forming a semiconductor device - Google Patents

Method of forming a semiconductor device Download PDF

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Publication number
KR960043030A
KR960043030A KR1019950012602A KR19950012602A KR960043030A KR 960043030 A KR960043030 A KR 960043030A KR 1019950012602 A KR1019950012602 A KR 1019950012602A KR 19950012602 A KR19950012602 A KR 19950012602A KR 960043030 A KR960043030 A KR 960043030A
Authority
KR
South Korea
Prior art keywords
forming
semiconductor device
mask
width
wafer substrate
Prior art date
Application number
KR1019950012602A
Other languages
Korean (ko)
Other versions
KR0172718B1 (en
Inventor
이근호
김명군
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950012602A priority Critical patent/KR0172718B1/en
Publication of KR960043030A publication Critical patent/KR960043030A/en
Application granted granted Critical
Publication of KR0172718B1 publication Critical patent/KR0172718B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Abstract

본 발명은 반도체 소자의 형성방법에 관한 것으로, 보다 구체적으로는 단차를 갖는 반도체 표면에 마스크 형성공정을 진행함에 있어서 발생하는 벌크 이펙트를 방지하고, 소자의 제조 수율을 향상시킬 수 있는 반도체 소자의 형상방법에 관한 것으로 반도체 소자의 형성방법에 있어서, 상부와 하부간의 두께차를 갖는 웨이퍼 상부에 패턴을 형성할 때, 두께차를 고려하여 패턴을 형성하기 위한 마스크 설계시 마스크의 단차에 따라 폭을 부분적으로 적절히 조절하여 패턴에 의한 식각 공정시 균일한 패턴을 이룸으로써, 디바이스 특성을 개선할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to a shape of a semiconductor device capable of preventing bulk effects occurring during the process of forming a mask on a semiconductor surface having a step, and improving the production yield of the device. In the method of forming a semiconductor device, when the pattern is formed on the wafer having a thickness difference between the top and bottom, the width is partially determined in accordance with the step of the mask in the mask design for forming the pattern in consideration of the thickness difference By properly adjusting to form a uniform pattern during the etching process by the pattern, it is possible to improve the device characteristics.

Description

반도체 소자의 형성방법Method of forming a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 실시예 1에 다른 마스크 제작 평면도, 제3도는 본 발명의 실시예 2에 따른 마스크 제작 평면도.2 is a plan view of manufacturing a mask according to Embodiment 1 of the present invention, and FIG. 3 is a plan view of manufacturing a mask according to Embodiment 2 of the present invention.

Claims (4)

단차부를 구비한 웨이퍼 기판에 포토 레지스트막을 코팅하고, 마스크를 사용하여 노광하고, 현상하여 포토 레지스트 패턴을 구성하는 반도체 소자의 형성방법에 있어서, 상기 마스크는 웨이퍼 기판상에 형성된 단차를 고려하여 설계 공정시 마스크의 폭을 부분적으로 확대시키거나, 축소시킴으로써 균일한 배선을 이루는 것을 특징으로 하는 반도체 소자의 형성방법.A method of forming a semiconductor device in which a photoresist film is coated on a wafer substrate having a stepped portion, exposed using a mask, and developed to form a photoresist pattern, wherein the mask is designed in consideration of the step formed on the wafer substrate. A method of forming a semiconductor device, characterized in that uniform wiring is achieved by partially enlarging or reducing the width of the mask. 제1항에 있어서, 상기 마스크는 웨이퍼 기판 상의 낮은 영역에 상당하는 마스크 패턴부분의 폭을 그의 높은 영역에 상당하는 마스크 패턴 부분의 폭보다 좁게 형성하는 것을 특징으로 하는 반도체 소자의 형성방법.The method of forming a semiconductor device according to claim 1, wherein the mask is formed such that the width of the mask pattern portion corresponding to the low region on the wafer substrate is narrower than the width of the mask pattern portion corresponding to the high region. 제1항에 있어서, 상기 웨이퍼 기판 상의 높은 영역에 상당하는 마스크 패턴부분의 폭을 그의 낮은 영역에 상당하는 마스크 패턴부분의 폭보다 넓게 형성하는 것을 특징으로 하는 반도체 소자의 형성방법.The method of forming a semiconductor device according to claim 1, wherein the width of the mask pattern portion corresponding to the high region on the wafer substrate is formed wider than the width of the mask pattern portion corresponding to the low region. 제1항 내지 제3항중 어느 한 항에 있어서, 상기 마스크 패턴의 조절 폭은 웨이퍼 기판상의 높은 영역과 낮은 영역과의 두께차에 의해 조절 가능한 것을 특징으로 하는 반도체 소자의 형성방법.The method of forming a semiconductor device according to any one of claims 1 to 3, wherein the adjustment width of the mask pattern is adjustable by a thickness difference between a high region and a low region on the wafer substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950012602A 1995-05-19 1995-05-19 Method of fabricating semiconductor device KR0172718B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950012602A KR0172718B1 (en) 1995-05-19 1995-05-19 Method of fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950012602A KR0172718B1 (en) 1995-05-19 1995-05-19 Method of fabricating semiconductor device

Publications (2)

Publication Number Publication Date
KR960043030A true KR960043030A (en) 1996-12-21
KR0172718B1 KR0172718B1 (en) 1999-03-30

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ID=19414950

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950012602A KR0172718B1 (en) 1995-05-19 1995-05-19 Method of fabricating semiconductor device

Country Status (1)

Country Link
KR (1) KR0172718B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100702114B1 (en) * 2000-11-17 2007-03-30 주식회사 하이닉스반도체 Method for solution gap of photoresist by photoresist processing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100702114B1 (en) * 2000-11-17 2007-03-30 주식회사 하이닉스반도체 Method for solution gap of photoresist by photoresist processing

Also Published As

Publication number Publication date
KR0172718B1 (en) 1999-03-30

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