KR960042906A

KR960042906A - Silicon On Insulator Wafer Labeling Method

Info

Publication number: KR960042906A
Application number: KR1019950011762A
Authority: KR
Inventors: 이병훈; 차기호; 이준희; 강치중
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-05-12
Filing date: 1995-05-12
Publication date: 1996-12-21

Abstract

실리콘 온 인슐레이터 웨이퍼의 라벨링 방법에 대해 기재되어 있다. 이는 핸들링 웨이퍼 상에 사진식각 공정으로 웨이퍼의 라벨을 새기는 제1공정, 상기 핸들링 웨이퍼의 전체면을 제1절연막으로 캐핑하는 제2공정, 그 상부에 제2절연막이 형성되어 있는 패터닝 웨이퍼를 상기 핸들링 웨이퍼에 본딩하는 제3공정, 상기 패터닝 웨이퍼의 가장자리를 연마하는 제4공정, 및 상기 제2절연막이 표면으로 드러날 때까지 상기 패터닝 웨이퍼의 표면을 식각용액으로 식각하는 제5공정을 포함하는 것을 특징으로 한다. 따라서, 라벨 인식과 웨이퍼 관리가 용이하고, 핸들링 웨이퍼의 스트레스 및 긁힘을 줄일 수 있다.A method of labeling a silicon on insulator wafer is described. This process includes a first step of engraving a label of a wafer by a photolithography process on a handling wafer, a second process of capping the entire surface of the handling wafer with a first insulating film, and handling the patterned wafer having a second insulating film formed thereon. A third step of bonding to the wafer, a fourth step of polishing the edges of the patterned wafer, and a fifth step of etching the surface of the patterned wafer with an etching solution until the second insulating layer is exposed to the surface; It is done. Thus, label recognition and wafer management are easy and stress and scratching of the handling wafer can be reduced.

Description

Silicon On Insulator Wafer Labeling Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2E도는 본 발명에 의한 실리콘 온 인슐레이터 웨이퍼의 라벨링 방법을 설명하기 위해 도시한 단면도들이다.2A to 2E are cross-sectional views illustrating a method for labeling a silicon on insulator wafer according to the present invention.

Claims

A first step of labeling the wafer by a photolithography process on the handling wafer; A second step of capping the entire surface of the handling wafer with a first insulating film; A third step of bonding a patterning wafer having a second insulating film formed thereon to the handling wafer; A fourth step of polishing an edge of the patterned wafer; And a fifth step of etching the surface of the patterned wafer with an etching solution until the second insulating layer is exposed to the surface.

The method of claim 1, wherein the fourth process is performed until the patterned wafer remains at a thickness of about 10 to 20 μm.

The method of claim 1, wherein the etching solution is a solution containing 15% KOH.

2. The labeling of a silicon on insulator wafer according to claim 1, further comprising, after the fifth step, back polishing the patterned wafer and chemically-mechanically polishing the back polished patterned wafer. Way.

※ Note: The disclosure is based on the initial application.