KR960039844A - Synchronous signal transmission control device of image display device - Google Patents
Synchronous signal transmission control device of image display device Download PDFInfo
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- KR960039844A KR960039844A KR1019950010273A KR19950010273A KR960039844A KR 960039844 A KR960039844 A KR 960039844A KR 1019950010273 A KR1019950010273 A KR 1019950010273A KR 19950010273 A KR19950010273 A KR 19950010273A KR 960039844 A KR960039844 A KR 960039844A
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Abstract
본 발명은 동기신호분리수단과 의사동기신호생성수단 사이에 멀티플렉서를 설치하여 화상신호의 입력여부에 상관없이 전원이 ON되어 있으면 그 멀티플렉서를 통해 동기신호분리수단 또는 의사동기신호생성수단으로 부터의 동기신호/의사동기신호를 항상 후단의 신호처리단으로 전송되도록 한 화상표시장치의 동기신호 전송제어장치를 제공하기 위한 것이다.The present invention provides a multiplexer between the synchronizing signal separating means and the pseudo synchronizing signal generating means and synchronizes from the synchronizing signal separating means or the pseudo synchronizing signal generating means through the multiplexer when the power is turned on regardless of whether the image signal is input. SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization signal transmission control apparatus of an image display device in which a signal / pseudosynchronous signal is always transmitted to a signal processing stage at a later stage.
이를 위해 본 발명은, 입력화상신호에서 동기신호를 각각 분리하는 동기신호분리부(10)와, 소정의 의사동기신호를 생성하는 의사동기신호생성수단(15), 상기 동기신호분리부(10)로부터의 수평동기신호를 수취하여 내부적인 기준클럭과 위상로크시키는 위상동기루프부(20), 상기 동기신호분리부(10) 또는 상기 의사동기신호생성수단(15)으로부터의 수평동기신호를 기준으로 수직동기신호를 분주하여 화소구동소자의 구동을 위한 기수필드 및 우수필드를 판별하는 필드판별부(25) 및 제어부(45)로부터의 시스템클럭신호를 기호로 상기 동기신호분리부(10) 또는 상기 의사동기신호생성수단(15)으로부터의 복합동기신호를 지연시키는 지연수단(30)을 갖춘 화상표시장치에서, 상기 동기신호분리부(10)와 상기 의사동기신호생성수단(15) 사이에 설치되어 상기 제어부(45)의 제어하에 상기 동기신호분리부(10) 또는 상기 의사동기신호생성수단(15)으로부터의 동기신호를 각각 대응되는 상기 위상동기루프부(20)와 상기 필드판별부(25) 및 상기 지연수단(30)으로 전송시키는 멀티플렉서(50)를 추가로 구비하고, 상기 제어부(45)는 상기 동기신호분리부(10)로 화상신호가 입력되는 경우에는 상기 동기신호분리부(10)에서 분리된 동기신호가 상기 위상동기루프부(20)와 상기 필드판별부(25) 및 상기 지연수단(30)으로 전송되도록 상기 멀티플렉서(50)를 제어하는 반면, 상기 동기신호분리부(10)로 화상신호가 입력되지 않는 경우에는 상기 의사동기신호생성수단(15)에서의 의사동기신호가 상기 위상동기루프부(20)와 상기 필드판별부(25) 및 상기 지연수단(30)으로 전송되도록 상기 멀티플렉서(50)를 제어하는 것이다.To this end, the present invention, the synchronization signal separation unit 10 for separating the synchronization signal from the input image signal, pseudo-synchronization signal generation means 15 for generating a predetermined pseudo synchronization signal, the synchronization signal separation unit 10 A horizontal synchronous signal from the phase synchronous loop unit 20, the synchronous signal separation unit 10, or the pseudo synchronous signal generating means 15 which receives the horizontal synchronous signal from the phase lock and phase locks the internal reference clock. The sync signal separating unit 10 or the system clock signal from the field discriminating unit 25 and the control unit 45 for discriminating the odd field and the even field for driving the pixel driver by dividing the vertical sync signal. In the image display apparatus having the delay means 30 for delaying the composite synchronous signal from the pseudo synchronous signal generation means 15, it is provided between the synchronous signal separation section 10 and the pseudo synchronous signal generation means 15. The control Under the control of 45, the phase synchronizing loop unit 20, the field discriminating unit 25, and the synchronizing signal from the synchronizing signal separating unit 10 or the pseudo synchronizing signal generating unit 15 respectively correspond. A multiplexer 50 is further provided for transmitting to the delay means 30, and the control unit 45 separates from the sync signal separator 10 when an image signal is input to the sync signal separator 10. FIG. The multiplexer 50 is controlled so that the synchronized signal is transmitted to the phase synchronization loop unit 20, the field discrimination unit 25, and the delay means 30, while the image is transmitted to the synchronization signal separator 10. When no signal is input, the multiplexer is configured to transmit the pseudo-synchronous signal from the pseudo-synchronous signal generating means 15 to the phase-locked loop part 20, the field discriminating part 25, and the delay means 30. 50 is to control.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 본 발명의 일실시예에 따른 화상표시장치의 동기신호 전송제어장치를 설명하는 블럭구성도.1 is a block diagram illustrating a synchronization signal transmission control apparatus of an image display apparatus according to an embodiment of the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950010273A KR960039844A (en) | 1995-04-28 | 1995-04-28 | Synchronous signal transmission control device of image display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019950010273A KR960039844A (en) | 1995-04-28 | 1995-04-28 | Synchronous signal transmission control device of image display device |
Publications (1)
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KR960039844A true KR960039844A (en) | 1996-11-25 |
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Family Applications (1)
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KR1019950010273A KR960039844A (en) | 1995-04-28 | 1995-04-28 | Synchronous signal transmission control device of image display device |
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KR (1) | KR960039844A (en) |
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1995
- 1995-04-28 KR KR1019950010273A patent/KR960039844A/en not_active Application Discontinuation
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