KR960038546A - Pulse width modulated signal generator - Google Patents

Pulse width modulated signal generator Download PDF

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Publication number
KR960038546A
KR960038546A KR1019950010184A KR19950010184A KR960038546A KR 960038546 A KR960038546 A KR 960038546A KR 1019950010184 A KR1019950010184 A KR 1019950010184A KR 19950010184 A KR19950010184 A KR 19950010184A KR 960038546 A KR960038546 A KR 960038546A
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KR
South Korea
Prior art keywords
signal
data
register
generating
microcomputer
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KR1019950010184A
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Korean (ko)
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KR0152344B1 (en
Inventor
표정철
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김광호
삼성전자 주식회사
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Priority to KR1019950010184A priority Critical patent/KR0152344B1/en
Publication of KR960038546A publication Critical patent/KR960038546A/en
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Publication of KR0152344B1 publication Critical patent/KR0152344B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야 마이컴의 인터페이스회로1. Interface circuit of the microcomputer of the technical field to which the invention described in the claims belongs

2. 발명이 해결하려고 하는 기술적 과제, 마이컴의 시스템클럭의 주기에 상관없이 마이컴에서 처리된 데이타를 정밀한 데이타로 변환하여 주변회로로 전달하는 펄스폭변조신호 발생회로를제공함에 있다.2. A technical problem to be solved by the present invention is to provide a pulse width modulated signal generating circuit for converting data processed by a microcomputer into precise data regardless of the period of a system clock of a microcomputer and transferring the data to a peripheral circuit.

3. 발명의 해결방법의 요지, 제1레지스터와 제2레지스터로 구성되며 마이컴에서 처리된 데이타중, 소정의 상위비트 데이타는 상기 제1레지스터에 저장하고, 상기 상기 비트데이타를 제외한 나머지 하위비트데이타는 상기 제2레지스터에 저장하는 레지스터수단과, 마이컴의 시스템클럭에 동기되어 카운팅동장을 하여 카운팅 데이타를 발생하며, 카운팅동작이 완료됐을 때 세트신호를 발생하는 카운터와; 상기 상위비트데이타와 카운팅 데이터타를 비교하여 일치하는 경우에 일치신호를 발생하는 비교수단과; 상기 하위비트 데이타를 아날로그 데이타로 변화하는 디지털/아날로그변환수단과; 상기 시스템클럭에 동기되어 삼각파를 발생하는 삼각파발생수단과; 상기 삼각파와 아날로그신호의 레벨을 비교하여 리세트신호를 발생하는 전압비교수단과; 상기 세트신호와 일치신호와 리세트신호를 인가받아 펄스폭변조 제어신호를 발생하는 펄스폭변조신호 제어수단으로 구성한다.3. Summary of Solution of the Invention Among the data processed by the microcomputer and composed of the first register and the second register, predetermined upper bit data is stored in the first register, and the remaining lower bit data except the bit data. A register means for storing in the second register, a counter synchronized with a system clock of the microcomputer to generate counting data, and a counter for generating a set signal when the counting operation is completed; Comparing means for comparing the higher bit data with the counting data and generating a matching signal when the same is matched; Digital / analog converting means for converting the lower bit data into analog data; Triangular wave generating means for generating triangular waves in synchronization with the system clock; Voltage comparing means for comparing a level of said triangular wave with an analog signal to generate a reset signal; And pulse width modulation signal control means for receiving the set signal, the coincidence signal, and the reset signal to generate a pulse width modulation control signal.

4. 발명의 중요한 용도, 마이컴의 인터페이스회로에 사용된다.4. It is an important use of the invention, it is used in the interface circuit of the microcomputer.

Description

펄스폭변조신호 발생회로Pulse width modulated signal generator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 펄스폭변조신호 발생회로의 구성도3 is a block diagram of a pulse width modulated signal generating circuit according to the present invention

Claims (3)

마이컴에서 처리된 데이타를 시스템 클럭주기에 상관없이 주변회로로 전달하는 인터페이스회로에 있어서, 제1레지스터와 제2레지스터로 구성되며, 마이컴에서 처리된 데이타중, 소정의 상위비트 데이타는 상기 제1레지스터에 저장하고, 상기상위 비트데이타를 제외한 나머지 하위비트데이타는 상기 제2레지스터에 저장하는 레지스터수단과; 마이컴의 시스템클럭 동기되어 카운팅동작을 하여 카운팅 데이타를 발생하며, 카운팅동작이 완료됐을 때 세트신호를 발생하는 카운터와; 상기상위비트 데이터와 카운팅 데이타를 비교하여 일치하는 경우에 일치신호를 발생하는 비교수단과; 상기 하위비트 데이타를 입력하여 리세트신호로 발생하는 리세트신호 발생수단과; 상기 세트신호와 일치신호와 리세트신호를 입력하여 펄스폭변조 제어수단를 발생하는 펄스폭변조신호 제어수단으로 구성됨을 특징으로 하는 펄스폭변조신호 발생회로.An interface circuit for transferring data processed by a microcomputer to a peripheral circuit regardless of a system clock period, comprising a first register and a second register, and among the data processed by a microcomputer, predetermined high-order bit data is the first register. Register means for storing the lower bit data except for the upper bit data in the second register; A counter for generating counting data by performing a counting operation in synchronization with the system clock of the microcomputer and generating a set signal when the counting operation is completed; Comparison means for comparing the high-bit data and the counting data and generating a match signal when they match; Reset signal generation means for inputting the lower bit data to generate a reset signal; And a pulse width modulation signal control means for inputting the set signal, the coincidence signal, and the reset signal to generate a pulse width modulation control means. 제1항에 있어서, 상기 리세트신호 발생수단이, 상기 하이위트 데이타를 아날로그 데이타로 변환하는 디지탈/아날로그변환수단과, 상기 시스템클럭의 하강에지에 동기되어 삼각파를 발생하는 삼각파발생수단과; 상기 삼각파와 아날로그신호의 레벨을 비교하여 리세트신호를 발생하는 전압비교수단으로 비교됨을 특징으로 하는 펄스폭변조신호 발생회로.2. The apparatus of claim 1, wherein the reset signal generating means comprises: digital / analog converting means for converting the high-wit data into analog data, and triangular wave generating means for generating a triangular wave in synchronization with a falling edge of the system clock; And a voltage comparison means for comparing the level of the triangle wave and the analog signal to generate a reset signal. 제1항에 있어서, 상기 펄스폭변조신호 제어수단이 상기 세트신호에 의해 세트된 펄스폭 변조신호를 발생하며, 상기 일치신호가 발생한 시점이후의 최초의 상기 리세트신호의 상승에지에 의해 상기 펄스폭 변조신호를 리세트시켜 출력함을 특징으로 하는 퍽스폭 변조신호발생회로.The pulse width modulation signal control means generates a pulse width modulation signal set by the set signal, and the pulse is caused by the rising edge of the first reset signal after the point of time when the coincidence signal is generated. A perks width modulation signal generation circuit comprising: reset and outputting a width modulation signal.
KR1019950010184A 1995-04-27 1995-04-27 Pwm signal generating circuit KR0152344B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950010184A KR0152344B1 (en) 1995-04-27 1995-04-27 Pwm signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950010184A KR0152344B1 (en) 1995-04-27 1995-04-27 Pwm signal generating circuit

Publications (2)

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KR960038546A true KR960038546A (en) 1996-11-21
KR0152344B1 KR0152344B1 (en) 1998-10-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100657162B1 (en) * 2001-04-26 2006-12-12 매그나칩 반도체 유한회사 Programmable pulse width modulation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100657162B1 (en) * 2001-04-26 2006-12-12 매그나칩 반도체 유한회사 Programmable pulse width modulation circuit

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KR0152344B1 (en) 1998-10-15

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