KR960036341A - Digital demodulator - Google Patents

Digital demodulator Download PDF

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Publication number
KR960036341A
KR960036341A KR1019950007027A KR19950007027A KR960036341A KR 960036341 A KR960036341 A KR 960036341A KR 1019950007027 A KR1019950007027 A KR 1019950007027A KR 19950007027 A KR19950007027 A KR 19950007027A KR 960036341 A KR960036341 A KR 960036341A
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South Korea
Prior art keywords
unit
output
coefficients
multiplexer
address
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KR1019950007027A
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Korean (ko)
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KR100327350B1 (en
Inventor
고일석
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구자홍
엘지전자 주식회사
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Priority to KR1019950007027A priority Critical patent/KR100327350B1/en
Publication of KR960036341A publication Critical patent/KR960036341A/en
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Publication of KR100327350B1 publication Critical patent/KR100327350B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/38—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0491—Circuits with frequency synthesizers, frequency converters or modulators

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

본 발명은 입력된 디지탈 신호를 정확히 판단하여 이를 복조하기 위한 디지탈 복조기에 관한 것으로, 종래 디지탈복조기는 이퀄라이져(1)와 디지탈복조부(2)가 각각 별개로 구비되므로서 회로가 복잡하고, 특히 이퀄라이져(1)에서 이전의 값을 이용하므로서 디지탈 신호판단이 어려운 문제점이 있었다. 본 발명은 이와같은 종래 문제점을 해결하기 위하여 이퀄라이져와 복조기를 일체화시켜 상기 이퀄라이져를 통해 변조하는 베이스신호를 이용하여 신호를 판단하므로서 보다 정확한 신호판단이 정확한 신호판단이 가능하도록 한 것으로 디지탈신호복조기에 적용한다.The present invention relates to a digital demodulator for accurately determining an input digital signal and demodulating the digital signal. In the related art, a digital demodulator is complicated by a circuit having an equalizer (1) and a digital demodulator (2). Using the previous value in (1), there was a problem that digital signal determination is difficult. The present invention is applied to the digital signal demodulator to more accurately determine the signal by determining the signal using the base signal modulated by the equalizer by integrating the equalizer and the demodulator to solve such a conventional problem. do.

Description

디지탈 복조기Digital demodulator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본발명 디지탈신호 복조를 위한 전체 블럭도, 제4도는 본발명 계수발생부의 상세블럭도.3 is an overall block diagram for demodulating the digital signal of the present invention, and FIG. 4 is a detailed block diagram of the present invention coefficient generator.

Claims (4)

디지탈 변조의 베이스신호가 샘플링된 값(μ1,μ2...μn)이 저장된 메모리부(11)에서 출력되는 샘플링된 값(μ1,μ2...μn)에 각각 판단계수(a1, a2...an)를 곱하여 입력된 디지탈기준시호의 개별시간신호(γn)를 판단한 값(γn)을 출력하는 멀티플렉서/어드레스부(12)와, 상기 멀티플렉서/어드레스부(12)에서 출력된 판단값(γn)과 입력된 개별시간신호(γn)의 차(en)를 계수발생부(14)에 인가하는 감산부(13)와, 상기 감산부(13)에서 감산출력된 차(en)를 입력받아 멀티플렉서/어드레스부(12)에서 필요한 판단계수(a1, a2...an)를 발생하는 계수발생부(14)로 구성된 디지탈복조기.Which the base signal of the digital modulation sampling values (μ 1, μ 2 ... μ n) the sampling value outputted from the memory unit 11 is stored (μ 1, μ 2 ... μ n) , each coefficient is determined in a multiplexer / address unit 12 for outputting a value γ n determined by multiplying (a 1 , a 2 ... a n ) by the individual time signal γ n of the input digital reference time signal, and the multiplexer / address A subtraction unit 13 for applying the difference e n between the determination value γ n outputted from the unit 12 and the inputted individual time signal γ n to the coefficient generator 14, and the subtraction unit ( A digital demodulator comprising a coefficient generator 14 which receives the difference e n subtracted and output from 13) and generates the necessary coefficients a 1 , a 2 ... a n in the multiplexer / address unit 12. . 제1항에 있어서, 멀티플렉서/어드레스부(12)는 메모리부(11)에서 출력되는 샘플링 값(μ1,μ2...μn)과 계수발생부(14)에서 발생하는 판단계수(a1, a2...an)를 서로 곱하여 출력하는 곱셈기(12A)(12B)(12N)와, 상기 곱셈기(12A)(12B)(12N)에서 곱셈출력된 신호를 합하여 개별시간신호(γn)의 판단값(γn)을 출력하는 합산기(12-1)로 구성된 것을 특징으로 디지탈복조기.The multiplexer / address unit 12 according to claim 1, wherein the multiplexer / address unit 12 includes a sampling value (μ 1 , μ 2 ... μ n ) output from the memory unit 11 and a determination coefficient a generated by the coefficient generation unit 14. 1, a 2 ... a n) a multiplier (12A) (12B) (12N ) , and a discrete time signal (γ summing the multiplied output signals from the multipliers (12A) (12B) (12N ) for outputting multiplied by each other n judgment value (γ n), the output digital demodulator characterized by consisting of a summer (12-1) for a). 제2항에 있어서, 계수발생부(14)는 감산부(13)에서 감산출력된 차(en)를 입력받아 판단계수(a1, a2...an)를 완화하여 멀티플렉서/어드레스부(12)에 인가하는 아답티브필터(14-1)와, 아답티브필터(14-1)를 통해 완화되어 출력된 판단계수(a1, a2...an)를 입력받아 복조수행 여부를 결정하는 결정회로(14-2)로 구성된 것을 특징으로 한 디지탈복조기.The multiplexer / address according to claim 2, wherein the coefficient generator 14 receives the difference e n subtracted and output from the subtractor 13 to relax the determination coefficients a 1 , a 2 ... a n . Demodulation is performed by receiving the adaptive filter 14-1 applied to the unit 12 and the determination coefficients a 1 , a 2 ... A n that are relaxed and output through the adaptive filter 14-1. A digital demodulator comprising a decision circuit (14-2) for determining whether or not. 제3항에 있어서, 결정회로(14-2)는 아답티브필터(14-1)에서 출력된 판단계수(a1, a2...an)를 수령했는지 판단하여 결정인에이블신호를 출력하는 컨버젼스검출기(14-2A)와, 컨버젼스검출기(14-2A)에서 출력된 결정인에이블신호가 액티브되어 출력되었으면 메모리(14-2C)에서 저장된 미리 알고있는 계수(b1, b2...bn)를 스캔할 수 있게 어드레스를 출력하여 완화된 판단계수(a1,a2,..an와 미리 알고있는 계수(b1, b2...bn의 에러를 계산하여 평균값을 구한후 가장작은값을 선택하여 맵핑된 디지탈결과를 결정값으로 출력하는 비교/결정회로(14-2B)로 구성된 것을 특징으로 하는 디지탈복조기.4. The decision circuit 14-2 according to claim 3, wherein the decision circuit 14-2 determines whether the decision coefficients a 1 , a 2, ... a n output from the adaptive filter 14-1 are received and outputs a decision enable signal. If the convergence detector 14-2A and the decision enable signal output from the convergence detector 14-2A are activated and outputted, the previously known coefficients b 1 , b 2 ... b n ) outputs an address so that it can be scanned to calculate the mean of the relaxed coefficients (a 1 , a 2 , .. a n) and the known coefficients (b 1 , b 2 ... b n) . And a comparison / decision circuit (14-2B) for selecting the smallest value and outputting the mapped digital result as a determination value. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950007027A 1995-03-30 1995-03-30 Digital demodulator KR100327350B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950007027A KR100327350B1 (en) 1995-03-30 1995-03-30 Digital demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950007027A KR100327350B1 (en) 1995-03-30 1995-03-30 Digital demodulator

Publications (2)

Publication Number Publication Date
KR960036341A true KR960036341A (en) 1996-10-28
KR100327350B1 KR100327350B1 (en) 2002-07-27

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