JPH0368586B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides a multilevel DPSK demodulation method (Differential
This relates to a receiver demodulation method used when transmitting data using Phase Shift Keying (differential phase keying).

(Prior art) There is a delayed detection method as one of the demodulation methods of the multilevel DPSK modulation system.
An example of this is disclosed in Publication No. 196657. An example of a disclosed receiver using a conventional delayed detection method for 4-level DPSK signals (Japanese Patent Application Laid-Open No. 196657/1983)
is shown in Figure 3. 1 is a received signal input terminal, 2 is a quadrature demodulator, 3 is a local oscillator, 4 and 5 are low-pass filters, 6 and 7 are analog delay circuits, 8, 9, 10,
11 is an analog multiplier, 12 is an analog adder,
13 is an analog subtracter, 14 and 15 are polarity determiners, and 16 and 17 are detection output terminals. The phase difference with respect to the specified time difference T is ±45° or ±
A received signal x(t) of the transmitted signal is phase-modulated to be 135° and is input to the quadrature demodulator 2 via the received signal input terminal 1. The orthogonal demodulator 2 orthogonally demodulates the received signal x(t) using the local oscillator 3, and outputs the in-phase component and orthogonal component of the complex low-band signal obtained by the orthogonal demodulation to the low-pass filters 4 and 5, respectively. The low-pass filters 4 and 5 are waveform shaping filters for removing harmonic components from the in-phase component signal and the orthogonal component signal from the orthogonal demodulator 2, and further removing intersymbol interference. Assuming that the signals y ₁ (t) and y _Q (t) output from the low-pass filters 4 and 5 are the first and second low-pass signals,
The first and second low-frequency signals are divided into two, one of the first low-frequency signals y ₁ (t) is delayed by the above-determined fixed time T in the analog delay circuit 6, and the second low-frequency signal One of the signals y _Q (t) is delayed by the same fixed time in the analog delay circuit 7. These delayed low frequency signals y ₁
(t-T) and _yQ (t-T) are the third and fourth signals. The analog multiplier 8 receives the first low frequency signal y ₁
(t) and the third low-frequency signal y ₁ (t-T), and the analog multiplier 10 outputs the second low-frequency signal y _Q (t) and the fourth low-frequency signal y _Q (t-T). They are multiplied together and the results are output to the analog adder 12, respectively.
Further, the analog multiplier 9 receives the first low frequency signal y ₁ (t)
and the fourth low-frequency signal y _Q (t-T), the analog multiplier 11 multiplies the second low-frequency signal y _Q (t) and the third low-frequency signal y ₁ (t-T), respectively. , and outputs the result to the analog subtracter 13. Analog adder 12 includes analog multiplier 8 and analog multiplier 1
The analog subtracter 13 subtracts the multiplication results of the analog multipliers 9 and 11, and the result z ₁ (t) is sent to the polarity determiner ₁₅ . ) is output to the polarity determiner 14. Polarity determiners 14 and 15 determine the polarity of the signals from analog adder 12 and analog subtracter 13, and output the determination results to detection output terminals 16 and 17.
Output to.

For example, the DPSK signal x(t)=A(t)・cos(ω _p t
+θ _j ) is input. However, A(t) is the amplitude. The output of local oscillator 3 is cos (ω _p t + φ)
Assuming that [φ is the initial phase of the local oscillator], the outputs of the low-pass filters 4 and 5 are expressed by the following equation.

Output of low-pass filter 4 y ₁ (t)=A(t)・[cos(θ _j −φ)]/2 …(1) Output of low-pass filter 5 y _Q (t)=A(t)・[ sin(θ _j -φ)]/2...(2) As a result of the multiplication, addition, and subtraction described above, the outputs of the analog adder 12 and analog subtracter 13 are determined if there are no errors or variations in the analog delay circuit or analog multiplier. It can be considered that A(t)=A(t-T),
It becomes as follows.

Output of analog adder 12 Z ₁ (t)=A(t) ²・[cos(θ _j −φ) cos(θ _j-1
−φ) +sin(θ _j −φ) sin(φ _j-1 −φ)]/4 =A(t) ²・[cos(θ _j −θ _j-1 )]/4 …(3) Analog subtractor 13 output Z ₂ (t)=A(t) ²・[sin(θ _j −φ)cos(θ _j-1
−φ) −cos(θ _j −φ) sin(θ _j-1 −φ)]/4 = A(t) ²・[sin(θ _j −θ _j-1 )]/4 …(4) (θ _j −θ _j-1 ) is 45°, −45°, 135°, −135
Since Z ₁ (t) and Z ₂ (t) take either +A(t) ² or −A(t) ² . Therefore, the phase difference can be detected by determining the polarity of equations (3) and (4). FIG. 4 shows the relationship between the polarity and phase difference output to the detection output terminals 16 and 17.

In addition, in the conventional technology, in order to increase the number of multi-values to four or more, the threshold value increases as the number of multi-values increases, so the circuit configuration after the orthogonal demodulator becomes complicated. The number of analog delay circuits and analog computing units used also increases.

(Problems to be Solved by the Invention) However, the above-mentioned DPSK signal demodulation method has the following problems.

If there is a delay error in the analog delay circuit or if there are variations in characteristics in the analog arithmetic unit, an error will occur between the output Z ₁ (t) of the analog adder 12 and the output Z ₂ (t) of the analog subtracter 13. This causes an error in the value of the detected phase difference. In particular, when the number of multivalues increases, the margin for noise decreases due to the error. Therefore, the analog delay circuit and analog arithmetic unit must be highly accurate, but the adjustment is complicated, and elements with low temperature characteristics and changes over time must be selected.

Further, as the number of multi-values increases, the number of thresholds also increases with the number of multi-values. Therefore, the number of analog delay circuits and analog multipliers for demodulation also increases.
There is a problem that the circuit configuration becomes complicated.

Therefore, an object of the present invention is to solve the above problems and provide a DPSK modulation method that is effective for communication systems.

(Means for Solving the Problems) In order to solve the problems of the prior art, the present invention provides digital information of n bits (n is a natural number).
In the DPSK demodulation method that receives and demodulates a ^2n- value multilevel differential phase modulated signal, the following means are provided.

The above-mentioned DPSK demodulation method includes an amplification means for amplifying a received signal, an orthogonal demodulation means for orthogonally demodulating the signal from the amplification means, and an in-phase component of a complex low-band signal obtained by orthogonal demodulation for each time slot. a first sampling means for sampling to obtain a first digital value; and a second sampling means for sampling at each time slot for orthogonal components of a complex low-frequency signal obtained by orthogonal demodulation to obtain a second digital value. a sampling means, a first device that stores amplitude and phase data, receives first and second digital values as address signals, and outputs both amplitude and phase data specified by the first and second digital values; storage means; control means for controlling the amplification means based on the time series of amplitude data output from the first storage means; and storage means for storing the phase data output from the first storage means over one time slot. and detecting means for detecting phase difference data between adjacent time slots by determining the difference between the phase data and the phase data stored one time slot before; data as a third digital value, and a second storage means that outputs n-bit digital information specified by the third digital value by inputting this digital value as an address signal. .

(Operation) According to the present invention, since the DPSK demodulation method is configured as described above, each technical means operates as follows.

The received data amplified by the amplification means is orthogonally demodulated by the orthogonal demodulation means. The first sampling means samples the in-phase component of the complex low-frequency signal obtained by orthogonal demodulation every time slot to obtain a first digital value. The second sampling means similarly samples the orthogonal component of the complex low-frequency signal at each time slot to obtain a second digital value. The first storage means stores amplitude and phase data and outputs amplitude and phase data specified by first and second digital values. The control means controls the amplifier circuit means based on the time series of amplitude data from the first storage means. The detection means receives the phase data from the first storage means.
The phase difference data between adjacent time slots is detected by storing the phase data over the time of the time slot and determining the difference between the phase data and the phase data stored one time slot before. The second storage means stores n-bit digital information, uses the phase data detected by the detection means as a third digital value, and outputs n-bit digital information specified by this digital value.

Therefore, the analog delay circuit and analog arithmetic unit as in the past are no longer necessary, and the detected phase difference is used as the address of the second storage means to output digital information corresponding to the phase difference. Even if the number of values increases, it is only necessary to rewrite the contents stored in the storage means without changing the circuit configuration. Therefore, the problems of the prior art can be solved.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a multilevel DPSK demodulator according to an embodiment of the present invention. In the same figure, 18 is an input terminal, 19 is an automatic gain control
AGC amplifier, 20 is a quadrature demodulator, 21 is a local oscillator, 22, 23 are low-pass filters, 24, 25 are sample and hold circuits, 26, 27 are analog-to-digital converters, 28, 34 are address generators,
29 and 35 are memory ROM, 30 is an AGC amplifier controller, 31 is a digital-to-analog converter, 32 is a shift register, 33 is a digital adder, 36
is the output terminal.

Next, the operation of this embodiment will be explained.

Multi-level DPSK signal x given from input terminal 18
(t) is an AGC amplifier 19, a quadrature demodulator 20, and a low-pass filter 2 that reduce input level fluctuations.
2 and 23, the complex low-frequency signal is separated into in-phase components and quadrature components. The low-pass filters 22 and 23 are waveform shaping filters. The in-phase component of the waveform-shaped complex low-frequency signal is sampled at each time slot by the sample-and-hold circuit 24, and then outputted by the analog-to-digital converter 26 as a first digital value _yIj . However, j=0, 1, 2
..., J, represents the sampling value of the j-th time slot. Similarly, the orthogonal components of the complex low-frequency signal whose waveforms have been shaped are sampled at each time slot by the sample-and-hold circuit 25, and then
The analog-to-digital converter 27 outputs the second digital value y _Qj (j=0, 1, 2, . . . , J). The first digital value y _lj and the second digital value are y _lj since y _Qj is the sampling value of the in-phase component and quadrature component of the complex low-frequency signal shown in equations (1) and (2). =Aj/2・cos(θ _j −φ) (j=0,1,2,…,J)……(5) y _Qj =−A _j /2・sin(θ _j −φ) (j=0 , 1, 2,..., J)...(6). Here, A _j is the amplitude and θ _j −φ is the phase. Therefore, A _j =2・(y _Ij ² +y _Qj ² ) ^1/2 ...(7) θ _j −φ=tan ⁻¹ (−y _Qj /y _Ij ) When y _Qj ≦0, π − tan ^{− 1} (−y _Qj /y _Ij ) When y _Qj > 0, the following relationship exists.

The first memory 29 stores the amplitude A _j for y _Ij and y _Qj .
This is a read-only memory ROM in which the values of phase θ _j −φ are calculated in advance using equations (7) and (8), and the results are written.

The first digital value y _Ij and the second digital value y _Qj are converted into the amplitude A j and phase _{θ j} corresponding to the values of y _Ij and y _Qj .
-φ is input to the first address generator 28 which converts it into the address code of the first memory 29 written in, the first memory 29 is accessed, and from the first memory, the amplitude A _j and the phase θ _j -φ is output at the same time. For example, as the data in the first memory 29,
The above can be easily achieved by assigning amplitude data to the upper bits and phase data to the lower bits.

Amplitude A _j is input to amplifier controller 30 .
The AGC amplifier controller 30 detects fluctuations in the amplitude A _j and generates a gain control signal for the AGC amplifier 19, which is then passed through the digital-to-analog converter 31.
It is input to the gain control input terminal of the AGC amplifier 19.

Phase data θ _j output from the first memory 29
-φ is divided into two parts, one of which is input to a shift register 32 that performs a delay operation, and the other to a digital adder 33. In the shift register 32,
In order to delay the data by the time T of one time slot, the input data is stored for the time T of one time slot, and then the sign of the data is inverted and output to the digital adder 33.

Therefore, the digital adder 33 adds the j-th phase θ _j −φ and the j-1-th phase −(θ _j-1 −φ) whose sign has been inverted. That is, the digital adder 33 outputs the value θ _j -θ _j-1 , and this phase difference is the phase difference between adjacent time slots. In the multilevel DPSK modulation method, n-bit (n=1, 2,...) digital information is transmitted in correspondence with the phase difference (θ _j -θ _j-1 ), so on the receiving side, this The transmitted information can be restored by performing the opposite operation, that is, converting the phase difference (θ _j -θ _j-1 ) into the corresponding n-bit digital information.

In the second address generator 34, the phase difference (θ _j −
θ _j-1 ) to generate an address code for the second memory 35 in which digital information corresponding to the phase difference is stored, and the second memory 35 reads out the digital information stored at the address. , outputs the code from the output terminal 36.

The relationship between the phase difference (θ _j −θ _j-1 ) and n-bit digital information is arbitrary, but here we will take the case of n = 2 as an example and use the so-called π/4 system Gray code as shown in Figure 2. Shown below. In this example, if the phase difference is between 0 and 1/2π, the code (00) is assigned,
Code data (00) is stored in the second memory 35 at addresses corresponding to the phase difference 0 to 1/2π.

(Effects of the Invention) As described above in detail, according to the present invention, the digital values of the orthogonal component and the in-phase component of the complex low-frequency signal obtained by orthogonal demodulation of the multilevel DPSK signal are converted into amplitude and phase data. This is used as an address signal for the first memory stored in the first memory, and the amplitude and phase data stored at the address are output. Since the phase difference between adjacent time slots is detected by calculating the difference with the phase data stored before the slot using a digital arithmetic unit, an analog delay circuit and an analog arithmetic unit are not required. Furthermore, the detected phase difference is used as an address signal for the second memory in which code data corresponding to the phase difference is stored, and the code data stored at the address is output, so that the multilevel number can be reduced. Even if it increases,
This has the advantage that it is only necessary to rewrite the memory in which the code data is stored, without changing the circuit configuration.

Furthermore, since amplitude data is also stored in the first memory, it is easy to add an AGC amplifier, which is necessary when the signal input level fluctuates greatly.
This has the advantage that it is easy to generate an optimal control signal according to the varying speed.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a DPSK signal demodulator according to an embodiment of the present invention, Fig. 2 is a diagram showing the relationship between phase difference and sign, and Fig. 3 is a delay detection circuit related to a conventional DPSK signal demodulator. A block diagram showing the configuration of
FIG. 4 is a diagram showing the relationship between detection output and phase difference. 18...Input terminal, 19...AGC amplifier, 2
0...Orthogonal demodulator, 21...Local oscillator, 22,
23...Low pass filter, 24, 25...Sample hold circuit, 26, 27...Analog-digital converter, 28, 34...Address generator, 2
9, 35...Memory ROM, 30...AGC amplifier controller, 31...Digital-to-analog converter, 3
2...Shift register, 33...Digital adder, 36...Output terminal.

Claims (1)

[Claims] 1 n bits (n is a natural number) of digital information
A DPSK demodulation method that receives and demodulates a signal subjected to multi-level differential phase modulation of 2 ⁿ values includes an amplifying means for amplifying the received signal, an orthogonal demodulating means for orthogonally demodulating the signal from the amplifying means, and an orthogonal demodulating means for orthogonally demodulating the signal from the amplifying means. a first sampling means for obtaining a first digital value by sampling the in-phase component of the complex low-frequency signal obtained by orthogonal demodulation in each time slot; a second sampling means for sampling every time slot to obtain a second digital value; and a second sampling means for storing amplitude and phase data, inputting the first and second digital values as address signals, and a first storage means for outputting both amplitude and phase data specified by digital values; a control means for controlling the amplification means based on the time series of the amplitude data output from the first storage means; The phase data output from the storage means is
Detecting means for storing phase data over a time slot and detecting phase difference data between adjacent time slots by determining the difference between the phase data and phase data stored one time slot before, and n-bit digital information. a second storage means that stores the phase difference data as a third digital value, and outputs n-bit digital information specified by the third digital value by inputting this digital value as an address signal; A DPSK demodulation method consisting of: