KR100327350B1 - Digital demodulator - Google Patents

Digital demodulator Download PDF

Info

Publication number
KR100327350B1
KR100327350B1 KR1019950007027A KR19950007027A KR100327350B1 KR 100327350 B1 KR100327350 B1 KR 100327350B1 KR 1019950007027 A KR1019950007027 A KR 1019950007027A KR 19950007027 A KR19950007027 A KR 19950007027A KR 100327350 B1 KR100327350 B1 KR 100327350B1
Authority
KR
South Korea
Prior art keywords
output
signal
coefficients
digital
unit
Prior art date
Application number
KR1019950007027A
Other languages
Korean (ko)
Other versions
KR960036341A (en
Inventor
고일석
Original Assignee
엘지전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지전자주식회사 filed Critical 엘지전자주식회사
Priority to KR1019950007027A priority Critical patent/KR100327350B1/en
Publication of KR960036341A publication Critical patent/KR960036341A/en
Application granted granted Critical
Publication of KR100327350B1 publication Critical patent/KR100327350B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/38—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0491—Circuits with frequency synthesizers, frequency converters or modulators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE: A digital demodulator is provided, which judges a signal accurately by judging a signal using a base signal modulated through an equalizer that is integrated with a demodulator. CONSTITUTION: A memory part(11) stores values(u1-un) that base signals of digital modulation are sampled. A multiplexor/address part(12) multiplies sampled values from the memory part(11) by judgement coefficients(a1-an) and outputs a value obtained by judging an individual time signal of an input digital reference signal. A subtraction part(13) applies an error(en) between a judgement value from the multiplexor/address part(12) and the input individual time signal to a coefficient generator part(14). The coefficient generator part(14) receives an output of the subtraction part to generate the judgement coefficients to be applied to the multiplexor/address part(12).

Description

디지탈 복조기Digital demodulator

본발명은 입력된 디지탈 신호를 정확히 판단하여 이를 복조하기 위한 디지탈 복조기에 관한것으로, 특히 각각의 이퀄라이져와 복조기를 일체화하여 상기 이퀄라이져에서 변조하는 베이스신호를 이용하여 신호를 판단하여 정확한 판단이 가능하도륵 한것이다.The present invention relates to a digital demodulator for accurately determining an input digital signal and demodulating it. In particular, an equalizer and a demodulator are integrated to judge a signal using a base signal modulated by the equalizer. It is.

종래 디지탈 복조기는 제1도에 도시된 바와같이, 채널폭이 제한된 디지탈 신호(γ)가 입력시 채널에 의한 왜곡을 정정하기 위한 이퀄라이져(1)와, 이퀄라이져(1)에서 채널왜곡이 정정된 디지탈신호()를 입력받아 각 베이스 신호와의 상호관계를 구한후 가장큰값을 이용하여 복조를 수행하는 디지탈복조부(2)로구성된 것이다.As shown in FIG. 1, a conventional digital demodulator has an equalizer 1 for correcting a distortion caused by a channel when a digital signal γ having a limited channel width is input, and a digital channel distortion corrected in the equalizer 1. signal( The digital demodulation unit 2 performs demodulation using the largest value after obtaining the mutual relationship with each base signal.

한 편, 이퀄라이져는 제2도에 도시된 바와같이 입력된 디지탈 기준신호인 개별시간신호(γn)와 합산기(6)에서 출력된 신호의차(e)를 계산하는 감산기(3)와, 감산기(3)에서 계산출력된 신호차(e)와 임의의계수(△)를 곱셈 출력하는 곱셈기(4)와, 상기곱셈기(4)에서 곱셈출력된 값과 입력된 디지탈 신호를 곱하여 누산기(5)에 인가하는 곱셈기(4A)와, 곱셈기(4A)에서 곱셈출력된 신호를 연산하는 누산기(5)와, 누산기(5)에서 연산 출력된 신호와 입력된 디지탈 신호를 곱하여 연산기(6)에 인가하는 곱셈기(4B)와, 상기 입력된 디지탈 신호를 각각 지연출력시키는 지연기(7)(7A)(7N)와, 상기 지연기(7)(7A)(7N)에서 지연출력된 디지탈 신호와 곱셈기(4)에서 곱셈 출력된 신호를 각 누산기(5A)(5N)에 인가하는 곱셈기(4C)(4N-1)와, 상기 누산기(5A)(5N)에서 연산출력된 신호와 지연기(7)(7N)에서 지연출력된 신호를 곱하여 합산기(6)에 인가하는 곱셈기(4D)(4N)와, 상기 각각의 곱셈기(4S)(4D)(4N)에서 곱셈출력된 신호를 합산하여 출력하는 합산기(6)로 구성된 것이다.On the other hand, the equalizer includes a subtractor 3 which calculates the difference e between the individual time signal γ n , which is an input digital reference signal, and the signal output from the summer 6, as shown in FIG. A multiplier 4 for multiplying and outputting the signal difference e calculated by the subtractor 3 and an arbitrary coefficient Δ, and a multiplier 5 by multiplying the value multiplied by the multiplier 4 with the input digital signal and accumulating the multiplier 5 Multiplier 4A to be applied to the multiplier, the accumulator 5 for calculating the signal multiplied by the multiplier 4A, and the digital signal inputted by the accumulator 5 and the input digital signal to be applied to the calculator 6. A multiplier (4B), a delay (7) (7A) (7N) for delaying the input digital signal, respectively, and a digital signal and a multiplier (Delay) output from the delay (7) (7A) (7N). A multiplier 4C (4N-1) for applying the signal multiplied by (4) to each accumulator 5A (5N), and the signal and delay unit 7 computed and output from the accumulator 5A (5N); ( A multiplier (4D) 4N for multiplying the delayed signal at 7N) and applying it to the summer 6, and summing and outputting the multiplied output signals from the respective multipliers 4S (4D) 4N. Group (6).

이와같이 구성된 종래 디지탈 복조기는 제l도에 도시된 바와같이 채널밴드폭이 제한된 경우 보통 이퀄라이져(1)를 통해 왜곡된 채널을 정정한후 디지탈복조부(2)를 통하여 채널왜곡이 정정된 디지탈 신호를 복조출력시킨다.As shown in FIG. 1, the conventional digital demodulator configured as described above demodulates a digital signal whose channel distortion is corrected through the digital demodulator 2 after correcting the distorted channel through the equalizer 1 when the channel bandwidth is limited. Output it.

한편 보통 이퀄라이져(1)는 제2도에 도시된 바와같이 각각의 곱셈기(4B)(4D)(4N)에서 곱셈출력된 신호를 합산기(6)가 모두 합산하여 현재의 신호를 판단출력시키면 디지탈복조부(2)는 상기 이퀄라이져(1)에서 합산출력된 신호를 입력받아 각 베이스신호와의 상호관계를 구한후 가장큰값을 이용하여 복조를 수행한다.On the other hand, in general, the equalizer 1 digitally adds the signals multiplied by the respective multipliers 4B, 4D, and 4N as shown in FIG. The demodulator 2 receives the sum signal output from the equalizer 1, finds a correlation with each base signal, and performs demodulation using the largest value.

그러나 종래 디지탈복조기는 이퀄라이져(1)와 디지탈복조부(2)가 각각 별개로 구비되므로서 회로가 복잡하고, 특히 이퀄라이져(1)에서 이전의 값을 이용하므로서 디지탈 신호판단이 어러운 문제점이 있었다.However, in the conventional digital demodulator, since the equalizer 1 and the digital demodulator 2 are provided separately, the circuit is complicated. In particular, the digital demodulator has a problem in that the digital signal judgment is difficult by using the previous value in the equalizer 1.

본 발명은 이와같은 종래 문제점을 해결하기 위하여 이퀄라이져와 복조기를 일체화시켜 상기 이퀄라이져를 통해 변조하는 베이스신호를 이용하여 신호를 판단하므로서 보다 정확한 신호판단이 가능하도록 한것으로 첨부된 도면에 의하여 본 발명의 구성및 작용효과를 설명하면 다음과 같다.The present invention is to solve the conventional problems by integrating the equalizer and the demodulator to determine the signal by using the base signal modulated through the equalizer to enable more accurate signal determination by the configuration of the present invention by the accompanying drawings and The following describes the working effect.

먼저 본발명 디지탈 복조기는 제3도에 도시된 바와같이 디지탈 변조의 베이스 신호가 샘플링된 값(μ1, μ2.... μn)이 저장된 메모리부(11)와, 메모리부(11)에서 출력되는 샘플링된 값(μ1, μ2.... μn)에 각각 판단계수(a1,a2.... an)를 곱하여 입력된 디지탈기준신호의 개별시간신호(γn)를 판단한값( n)을 출력하는 멀티플렉서/어드레스부(12)와, 상기 멀티플렉서/어드레스부(12)에서 출력된 판단값( n)과 입력된 개별시간신호(γn)의 차(en)를 계수발생부(14)에 인가하는 감산부(13)와,상기 감산부(13)에서 감산출력된 차(en)를 입력받아 멀티플렉서/어드레스부(12)에서 필요한 판단계수(a1,a2.... an)를 발생하는 계수발생부(14)로 구성된 것으로, 상기 멀터플렉서/어드레스부(12)는 메모리부(11)에서 출력되는 샘플링된값(μ1,μ2, .... μn)과 계수발생부(14)에서 발생하는 판단계수(a1,a2, .... an)를 서로 곱하여 출력하는 곱셈기(12A)(12B)(12N)와, 상기 곱셈기(12A)(12B)(12N)에서 곱셈출력된 신호를 합하여 개별시간신호(γn)의 판단값(n)을 출력하는 합산기(12-1)로 구성된 것이다.First, with the present invention a digital demodulator is a digital modulation of a base signal sampled values as shown in FIG. 3 (μ 1, μ 2 μ .... n) are stored in the memory unit 11, memory unit 11, The individual time signal (γ n ) of the input digital reference signal is multiplied by multiplying the sampled values (μ 1 , μ 2 .... μ n ) by the judgment coefficients (a 1 , a 2 .... a n ) respectively. ) n ), and the multiplexer / address unit 12 for outputting the judgment value (outputted from the multiplexer / address unit 12) ( n ) and a subtractor 13 for applying the difference e n between the inputted individual time signal γ n to the coefficient generator 14 and the difference e n subtracted and output from the subtractor 13. The multiplier / address unit 12 is configured as a coefficient generator 14 for generating the necessary coefficients (a 1 , a 2 .... a n ) in the multiplexer / address unit 12. Are sampled values (μ 1, μ 2 ,... N n ) output from the memory unit 11 and the determination coefficients a 1 , a 2 , .... a generated from the coefficient generator 14. The multiplier 12A, 12B, 12N multiplying each other by n and the signals multiplied and output by the multipliers 12A, 12B, 12N are added together to determine the determined value of the individual time signal γ n . and a summer 12-1 that outputs n).

제4도는 본 발명 계수발생부(14)의 블럭도로서, 감산부(13)에서 감산출력된 차(en)를 입력받아 판단계수(a1,a2.... an)를 완화하여 멀티플렉서/어드레스부(12)에 인가하는 아답티브필터(14-1)와, 아답티브필터(14-1)를 통해 완화되어 출력된 판단계수(a1,a2....an)를 입력받아 복조수행 여부를 결정하는 결정회로(14-2)로 구성된 것이다.4 is a block diagram of the coefficient generator 14 of the present invention. The difference coefficient n is subtracted and output from the subtractor 13 is received to relax the judgment coefficients a 1 , a 2. ahdap the capacitive filter 14-1, and a ahdap is relaxed via the capacitive filter 14-1, the output determination coefficient (a 1, a 2 .... a n) to be applied to the multiplexer / address section 12 It is composed of a decision circuit 14-2 that receives the input and determines whether to perform demodulation.

제5도는 결정회로(14-2)의 상세블럭도로서, 아답티브필터(14-1)에서 출력된 판단계수(a1,a2....an)를 수령했는지 판단하여 결정인에이블신호를 출력하는컨버젼스 검출기(14-2A)와, 컨버젼스검출기(14-2A)에서 출력된 결정인에이블신호가 액티브되어 출력되었으면 메모리(14-2C)에 저장된 미리 알고있는 계수(b1,b2.... bn)를 스캔할수있게 어드레스를 출력하여 완화된 판단계수(a1,a2....an)와 미리 알고있는계수(b1,b2....bn)의 에러를 계산하여 평균값을 구한후 가장작은값을 선택하여 맵핑된 디지탈결과를 결정값으로 출력하는 비교/결정회로(14-2B)로 구성된 것이다.5 is a detailed block diagram of the decision circuit 14-2. It is determined by determining whether the judgment coefficients a 1 , a 2 ... A n output from the adaptive filter 14-1 are received. Known coefficients b 1 and b 2 stored in the memory 14-2C when the convergence detector 14-2A for outputting the signal and the decision enable signal output from the convergence detector 14-2A are activated and output. .... b n) to be able to scan the determined coefficient mitigation outputs an address (a 1, a 2 .... a n) and the previously known coefficient (b 1, b 2 .... b n) , which It is composed of a comparison / decision circuit 14-2B that calculates an error, calculates an average value, selects the smallest value, and outputs the mapped digital result as a determination value.

이와같이 구성된 본 발명의 작용효과는 제3도 내지 제5도에 도시된 바와같이 디지탈기준신호인 개별시간신호(γn)가 입력되면, 메모리부(11)에는 디지탈 변조의 베이스신호가 샘플링된 값(μ1, μ2.... μn)이 저장되어 있으므로 상기 입력된 개별시간신호(γn)는 동일한 샘플링주파수로 샘플링되어야 한다.The operation and effect of the present invention configured as described above is a value obtained by sampling the base signal of digital modulation into the memory unit 11 when the individual time signal γ n , which is a digital reference signal, is input as shown in FIGS. 3 to 5. Since (μ 1 , μ 2 ... μ n ) are stored, the input individual time signal γ n should be sampled at the same sampling frequency.

따라서 메모리부(11)에 저장된 샘플링된 값(μ1, μ2... μn)이 출력되면 멀티플렉서/어드레스부(12)는 이를 입력받아 계수발생부(14)에서 출력된 판단계수(a1,a2.... an)를 곱하여 개별시간신호(γn)를 판단한 값( n)을 출력한다.Accordingly, when the sampled values (μ 1 , μ 2 ... μ n ) stored in the memory unit 11 are output, the multiplexer / address unit 12 receives the determination coefficients (a) output from the coefficient generator 14. 1, a 2 .... a n multiplied by a) determining the respective time signals (γ n) value ( outputs n ).

즉, 멀티플렉서/어드레스부(12)내의 곱셈기(12A)(12B)(12N)에 입력된 샘플링 값(μ1, μ2.... μn)을 각각의 판단계수(a1,a2.... an)와 곱하여 이를 합산기(12-1)에서 합산한 개별시간신호(γn)의 판단값( n)을 출력하면 감산부(13)는 입력된 디지탈 기준신호의 개별시간신호(γn)에서 판단값( n)을 감산하여 상기 감산된 에러값(en)를 계수발생부(14)에 인가한다.That is, the sampling values (μ 1 , μ 2 ... Μ n ) input to the multipliers 12A, 12B, 12N in the multiplexer / address unit 12 are determined by the respective judgment coefficients a 1 , a 2 . ... the determined value of the individual time signal γ n multiplied by a n ) and summed in summer 12-1 n) from the subtracting unit 13 each time the signal (γ n) of the input digital reference signal when the output determination value ( n ) is subtracted to apply the subtracted error value e n to the coefficient generator 14.

이와같이 감산부(13)에서 감산출력된 에러값(en)를 이용하여 계수발생부(14)에서 발생하는 판단계수(a1,a2.... an)를 계속 수정하여 이를 일정한 값으로 컨버젼하므로서 현재 리시브된 신호를 복조할수 있다.In this way determines the coefficient generated in coefficient generator 14 using a subtraction output an error value (e n) from the subtracting unit (13) (a 1, a 2 .... a n) continues to modify this predetermined value You can demodulate the currently received signal by converting it to.

모든 디지탈신호 방법은 메모리(11)에 저장된 샘플링된 값(μ1.... μn)이 언제나 동일한 캐리어신호인 CosWct와 SinWct로 구성되어 있고 보통 계수(a1,a2)의 차이이므로 입력된 판단한( n)을 정상화시켜 상기 계수(a1,a2)를 구하면 이로써 신호를 복조할수 있다.All digital signal methods are inputted because the sampled values (μ 1 .... μ n ) stored in the memory 11 are always composed of the same carrier signals CosWct and SinWct and are usually the difference between coefficients (a 1 , a 2 ) Judged By normalizing n ) to obtain the coefficients a 1 and a 2 , the signals can be demodulated.

예로서 두개의 반대신호인경우 a2=0이고,또는일때이므로 디지탈신호 "1"이 전송된 것이고,일때 디지탈신호 "0"이 전송된 것이다.For example, two opposite signals a 2 = 0, or when Digital signal "1" has been transmitted, Digital signal "0" is transmitted.

이를 다른 신호방법으로 확장할수 있다.This can be extended to other signaling methods.

즉, 계수발생부(14)내의 결정회로(14-2)에 있는 메모리(14-2C)에 저장된 미리 알고있는 계수를 b1,b2....bn라 하고, 컨버젼 된 계수를 a1,a2....an이라 할때 │ b1- a1│=ε1, .... │bn-an│=εn이라하고, 상기 ε1... εn이 가장작은값를 선택하여 이때의 미리 알고있는 계수(b1.... bn)를 이용하므로서 복조를 수행할수 있다.That is, the previously known coefficients stored in the memory 14-2C in the decision circuit 14-2 in the coefficient generator 14 are b 1 , b 2 .... b n , and the converted coefficients are a 1 , a 2 .... a n │ b 1 -a 1 │ = ε 1 , .... │ b n -a n │ = ε n , and ε 1 ... ε n is By selecting the smallest value, demodulation can be performed by using the known coefficients (b 1 .... b n ) at this time.

제4도는 본 발명 계수발생부(14)의 상세블럭도로서 아답티브필터(14-1)는 판단계수(a1,a2... an)를 완화하여 멀티플렉서/어드레스부(12)에 인가하는 회로이고, 결정회로(14-2)는 완화되어 출력된 판단계수(a1,a2... an)를 이용하여 복조수행여부를 결정하는 회로이다.4 is a detailed block diagram of the coefficient generator 14 of the present invention, and the adaptive filter 14-1 relaxes the coefficients of determination a 1 , a 2 ... a n to the multiplexer / address unit 12. The decision circuit 14-2 is a circuit for applying demodulation by using the relaxed coefficients a 1 , a 2 ... a n .

제5도는 결정회로(14-2)의 상세블럭도로서, 컨버젼스검출기(14-2A)는 아답티브필터(14-1)에서 출력된 판단계수(a1,a2... an)가 수렴했는지를 판단하여 결정인에이블 신호를 출력하는 것으로, 임의의 에러(ε)를 초기에 정의하고<ε인지 결정하여 조건에 맞을경우 컨버젼스할것으로 판단하여 결정인에이블을 액티브되게 출력시킨다.FIG. 5 is a detailed block diagram of the decision circuit 14-2. The convergence detector 14-2A determines that the determination coefficients a 1 , a 2 ... a n output from the adaptive filter 14-1 are determined. Determination of convergence and outputting a decision enable signal. An arbitrary error (ε) is initially defined and If it is <ε, it decides to converge when the condition is met and outputs the decision enable active.

따라서 결정인에이블신호가 액티브되게 출력되있으면 컨버젼스검출기(14-2A)는 액티브되어 디코딩이 수행되고, 메모리(14-2C)에 저항된 미리 알고있는 계수의 모든 영역을 스캔할수 있도록 어드레스 출력하면서 계속적으로 완화된 판단계수(a1.... an)와 미리 알고있는 계수(b1... bn)의 에러를 계산한후 계산된 에러의 평균값을 구하여 이중 가장작은 평균값을 선택하여 상기 선택된 평균값에 맵핑된 디지탈 시퀀스(Sequence)를 결정값으로 출력한다.Therefore, if the decision enable signal is outputted as active, the convergence detector 14-2A is activated and decoded, and the address is output continuously so as to scan all regions of the known coefficients which are resisted in the memory 14-2C. Calculate the error of the coefficients of relaxation (a 1 .... a n ) and the known coefficients (b 1 ... b n ), and obtain the average of the calculated errors. The digital sequence mapped to the selected mean value is output as a determined value.

이상에서 설명한 바와같이 각각의 이퀄라이져와 복조기를 일체화하여 상기 이퀄라이져에서 변조되는 베이스신호를 이용하여 입력된 디지탈신호 보다 정확하게 판단가능하도록 하므로서 적은 BPS를 갖는 통신에 효율적으로 적용할수 있고 특히 채널왜곡이 큰 곳에 보다 효율적으로 이용할수 있으며 DSP칩을 이용한 소프트웨어로 구성하기에 보다 좋은 구조를 가지고 있다.As described above, each equalizer and demodulator are integrated so that the digital signal can be judged more accurately than the input digital signal by using the base signal modulated by the equalizer. It can be used more efficiently and has better structure to be composed by software using DSP chip.

제1도는종래 디지탈신호 복조를 위한 전제 블럭도Figure 1 is a block diagram of conventional digital signal demodulation

제2도는 종래 이퀄라이져 회로도2 is a conventional equalizer circuit diagram

제3도는 본발명 디지탈신호 복조를 위한 전체 블럭도3 is an overall block diagram for digital signal demodulation of the present invention.

제4도는 본발명 계수발생부의 상세블럭도4 is a detailed block diagram of the coefficient generator of the present invention

제5도는 본발명 계수발생부내의 결정회로 구조를 보인 상세블럭도5 is a detailed block diagram showing the structure of the crystal circuit in the coefficient generator according to the present invention.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

11; 메모리부 12; 멀티플렉서/어드레스부11; Memory section 12; Multiplexer / Address Section

13; 감산부 14: 계수발생부13; Subtraction section 14: counting section

Claims (4)

디지탈 변조의 베이스신호가 샘플링된 값(μ1, μ2.... μn)이 저장된 메모리부(11)에서 출력되는 샘플링된 값(μ1, μ2.... μn)에 각각 판단계수(a1, a2... an)를 곱하여 입력된 디지탈기존신호의 개별시간신호(γn)를 판단한 값( n)을 출력하는 멀티플렉서/어드레스부(l2)와, 상기 멀티플렉서/어드레스부(12)에서 출력된 판단값( n)과 입력된 개별시간신호(γn)의 차(en)를 계수발생부(14)에 인가하는 감산부(13)와, 상기 감산부(13)에서 감산출력된 차(en)를 입력받아 멀티플렉서/어드레스부(12)에서 필요한 판단계수(a1,a2... an)를 발생하는 계수발생부(14)로 구성된 디지탈복조기.To the sampled values (μ 1 , μ 2 .... μ n ) output from the memory unit 11 in which the digital signals are sampled (μ 1 , μ 2 .... μ n ). The value obtained by determining the individual time signal γ n of the digital existing signal input by multiplying the determination coefficients a 1 , a 2 ... a n ( n ) outputs a multiplexer / address unit l2 for outputting the determined value, and the determination value output from the multiplexer / address unit 12 ( n ) and a subtraction unit 13 for applying the difference e n between the inputted individual time signal γ n to the coefficient generation unit 14 and the difference e n subtracted and output from the subtraction unit 13. A digital demodulator comprising a coefficient generator (14) receiving the input and generating the necessary coefficients (a 1 , a 2 ... a n ) in the multiplexer / address unit (12). 제1항에 있어서, 멀티플렉서/어드레스부(12)는 메모리부(11)에서 출력되는 샘플링 값(μ1, μ2.... μn)과 계수발생부(14)에서 발생하는 판단계수(a1, a2.... an)를 서로 곱하여 출력하는 곱셈기(12A)(12B)(12N)와, 상기 곱셈기(12A)(12B)(12N)에서 곱셈출력된 신호를 합하여 개별시간신호(γn)의 판단값( n)을 출력하는 합산기(12-1)로 구성된 것을 특징으로한 디지탈복조기.The multiplexer / address unit 12 according to claim 1, wherein the multiplexer / address unit 12 includes a sampling value (μ 1 , μ 2 ... N n ) output from the memory unit 11 and a determination coefficient generated from the coefficient generator 14. a 1 , a 2 .... multiplier 12A, 12B, 12N multiplying and outputting a n ), and the signals multiplied and output by the multiplier 12A, 12B, 12N to add up individual time signals. judgment of (γ n ) ( n ) a digital demodulator, characterized by consisting of a summer 12-1. 제1항에 있어서, 계수발생부(14)는 감산부(13)에서 감산출력된 차(en)를 입력받아 판단계수(a1,a2.... an)를 완화하여 멀티플렉서/어드레스부(12)에 인가하는 아답티브필터(14-1)와, 아답티브필터(14-1)를 통해 완화되어 출력된 판단계수(a1, a2... an)를입력받아 복조수행 여부를 결정하는 결정회로(14-2)로 구성된 것을 특징으로한 디지틸복조기.The method of claim 1, wherein the coefficient generator 14 to reduce the determined coefficient (a 1, a 2 .... a n) receiving the difference (e n), the subtraction output from the subtraction unit 13, the multiplexer / Demodulates the adaptive filter 14-1 applied to the address unit 12 and the determination coefficients a 1 , a 2 ... a n that are relaxed and output through the adaptive filter 14-1. A digital demodulator comprising a decision circuit (14-2) for determining whether to perform. 제3항에 있어서, 결정회로(14-2)는 아답티브필터(14-1)에서 출력된 판단계수(a1, a2.... an)를 수령했는지 판단하여 결정인에이블신호를 출력하는컨버젼스검출기(14-2A)와, 컨버젼스검출기(14-2A)에서 출력된 결정인에이블신호가 액티브되어 출력되었으면 메모리(14-2C)에 저장된 미리 알고있는 계수(b1, b2.... bn)를 스캔할수있게 어드레스를 출력하여 완화된 판단계수(a1, a2.... an)와 미리 알고있는 계수(b1, b2.... bn)의 에러를 계산하여 평균값을 구한후 가장작은값을 선택하여 맵핑된 디지탈결과를 결정값으로 출력하는 비교/결정회로(14-2B)로 구성된 것을 특징으로한 디지탈 복조기.4. The decision circuit 14-2 determines whether the decision circuit 14-2 receives the decision coefficients a 1 , a 2 ... A n output from the adaptive filter 14-1. Known coefficients b 1 , b 2 ... Stored in memory 14-2C when the output of convergence detector 14-2A and the decision enable signal output from convergence detector 14-2A are activated and output. error .. b n) to be able to mitigate the determined coefficient outputs an address (a 1, scans a 2 .... a n) and the previously known coefficient (b 1, b 2 .... b n) , which And a comparison / decision circuit (14-2B) for outputting the mapped digital result as a determination value by selecting the smallest value after calculating the average value.
KR1019950007027A 1995-03-30 1995-03-30 Digital demodulator KR100327350B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950007027A KR100327350B1 (en) 1995-03-30 1995-03-30 Digital demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950007027A KR100327350B1 (en) 1995-03-30 1995-03-30 Digital demodulator

Publications (2)

Publication Number Publication Date
KR960036341A KR960036341A (en) 1996-10-28
KR100327350B1 true KR100327350B1 (en) 2002-07-27

Family

ID=37478397

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950007027A KR100327350B1 (en) 1995-03-30 1995-03-30 Digital demodulator

Country Status (1)

Country Link
KR (1) KR100327350B1 (en)

Also Published As

Publication number Publication date
KR960036341A (en) 1996-10-28

Similar Documents

Publication Publication Date Title
US8285239B2 (en) Receiver second order intermodulation correction system and method
KR100295513B1 (en) Spectrum direct spread signal receiver and acquisition circuit
JP3228353B2 (en) Demodulation method and apparatus with adaptive phase control
KR100581059B1 (en) Appratus and its Method for I/Q Imbalance Compensation by using Variable Loop Gain in Demodulator
US6275521B1 (en) Demodulating apparatus and demodulating method
KR100355502B1 (en) Ofdm communication apparatus and method thereof
US20060029158A1 (en) Amplitude peak cancellation
US7155245B2 (en) Multipath distortion eliminating filter
US8798125B2 (en) Phase tracking in communications systems
JP3576410B2 (en) Receiving apparatus, transmitting / receiving apparatus and method
JPH10233817A (en) Automatic gain control method and device for quadrature phase shift keying demodulator
US6330273B1 (en) Apparatus for code tracking in a direct sequence spread spectrum receiver
US20040127188A1 (en) Direct conversion receiver
KR100327350B1 (en) Digital demodulator
JP3073919B2 (en) Synchronizer
US8374287B2 (en) FM detector, signal interpolation method, and related program
JP4288458B2 (en) Amplitude limiting circuit and CDMA communication apparatus
US7145942B1 (en) Radio receiving system
JP3237628B2 (en) Channel characteristics estimator
JP3630581B2 (en) Spread modulation signal receiver
EP1508970B1 (en) Multipath distortion eliminating filter
JP3688395B2 (en) TDMA data receiver
JP2003134060A (en) Circuit and method for measuring ratio between desired wave power and interference wave power
JP4546230B2 (en) Demodulator
GB2298110A (en) Apparatus for providing code tracking in a direct sequence spread spectrum receiver

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070130

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee