GB2298110A

GB2298110A - Apparatus for providing code tracking in a direct sequence spread spectrum receiver

Info

Publication number: GB2298110A
Application number: GB9502992A
Authority: GB
Inventors: Anthony Peter Hulbert; David Peter Chandler
Original assignee: Roke Manor Research Ltd
Current assignee: Roke Manor Research Ltd
Priority date: 1995-02-16
Filing date: 1995-02-16
Publication date: 1996-08-21
Anticipated expiration: 2015-02-16
Also published as: CA2250074C; BR9612584A; GB9502992D0; GB2298110B; CN1220061A; CA2250074A1

Abstract

The apparatus comprises a frequency converter 4 for converting a received signal into inphase and quadrature signals. These signals are applied via analogue to digital converters 6, 8 to first 10-16, second 22-28 and third 36-42 correlators arranged to generate prompt, late and early signals respectively. Each correlator includes two multipliers and these are controlled by a code generator 56 via a circuit 58 for generating early, late and prompt signal codes. The output from the first correlator is passed to estimation means 18, 20 and signals generated from the estimation means are multiplied 30, 32, 44, 46 with the outputs from the first and second correlators in respect of each channel. The inphase and quadrature channel signals generated from the second and third correlators are added together 34, 48 and the sum signals are then subtracted 50 to generate a signal for controlling a loop filter 52 and a clock generation means 54 which controls the analogue to digital converters. In an alternative embodiment (Fig 3) the first correlator is not subjected to an estimation means, however the output signals from the inphase and quadrature channels are applied to a frequency phase discrimination means (76) which generates a control signal for controlling the frequency converter. In this way the coherent signal is all contained on one channel, for example, the inphase channel. The second and third correlators only comprise a single multiplier and accumulator and the output from these correlators are subtracted to generate a signal for controlling a loop filter and a clock generator which controls the analogue to digital converters.

Description

APPARATUS FOR PROVIDING CODE TRACKING IN A DIRECT SEQUENCE SPREAD SPECTRUM RECEIVER This relates to receivers for direct sequence spread spectrum and is concerned with code tracking part of the receiving apparatus.

The normal implementation of a code tracking device for spread spectrum consists of a so called early prompt late tracking loop and this involves energy detection of the correlated wave form for a correlation that is performed early, normally half a chip early, and a correlation of energy for a chip that is performed late, normally half a chip late. A timing discrimination curve is then generated by subtracting the early from the late and this is used to close a feedback loop to adjust the time, such that the prompt occurs at the correct time.

An aim of the invention is to remove the need to have the early and late correlations taking place at half a chip but specifically, to enable them to be applied at plus or minus one chip. This results in particular difficulties in the nonnal implementation, in that at plus or minus one chip for a circuit that is operating at the nominal timing, the correlation falls to zero and therefore energy detection of the signals will tend to be very noisy and thus a normal implementation would lead to a discrimination curve that is itself very noisy and would lead to a very jittery timing loop.

The apparatus uses spread spectrum signals which have been Nyquist filtered and therefore it uses signals, the correlation functions of which still has a good slope on it through the zero points and the basic problems are solved by not performing energy detection on the measurements taken or the correlations taken at these intervals but rather, coherently compensating them against a phase reference derived from the prompt signal and thereby reducing the effect of the noise and thus enabling a discrimination signal to be derived which is of a similar signal to noise ratio as would obtained in the more conventional plus or minus half a chip early/late situation.

According to one embodiment of the present invention there is provided apparatus for code tracking in a direct sequence spread spectrum receiver, comprising means for receiving a signal, means for converting the received signal into an inphase and quadrature signal, analogue to digital converter means per converting the inphase and quadrature signals into digital signals, a first correlator for handling prompt signals, a second correlator for handling late signals, a third correlator for handling early signals, estimation means for obtaining estimates of the output signals from the first correlator, first and second multiplying and adding means for multiplying the estimates with the output signals from the second and third correlators respectively and adding the inphase and quadrature channels together, subtraction means for subtracting the result from said first and second multiplying means, and control means arranged to receive the output signal from said subtracting means and generate control signals for the analogue to digital converter means.

According to another embodiment of the present invention there is provided apparatus for code tracking in a direct sequence spread spectrum receiver, comprising means for receiving a signal, converting means for converting the received signal into an inphase and quadrature signal, analogue to digital converter means for converting the inphase and quadrature signals into digital signals, a first complex correlator for handling prompt signals, a second correlator for handling late signals, a third correlator for handling early signals, a frequency phase discrimination means for receiving the signals from said first correlator and generating a signal for controlling said converting means in a manner such that a coherent signal is contained on one signal phase channel, subtractor means for subtracting the output signals from said second and third correlators, and control means connected to said subtractor means for controlling said analogue to digital converters.

Various embodiments of the present invention will now be described with reference to the accompanying drawings wherein; FIGURE 1 shows a typical correlation function for the output of a correlator, FIGURE 2 shows a block diagram of a first embodiment of the invention, and, FIGURE 3 shows a block diagram of a second embodiment of the invention.

Referring to Figure 1 a typical correlation function for the output of a correlator is shown, indicating the normal nominal positions for the early, late and prompt correlations, as well as the new proposed positions for the early and late positions, the prompt positions obviously being the same.

Referring to Figure 2, signal input generation means 2 shown as an antenna feeds a frequency converter means 4, which generates I and Qsignals which feed into a pair of analogue to digital converters 6, 8. The output of these feed into three half complex correlators. The correlator comprising units 10, 12, 14, 16 is for the prompt position, thus the I sample signal of the output of the converter 6 is multiplied by the prompt code in the multiplier 10 and is accumulated in the accumulator 14, and similarly for multiplier 12, and accumulator 16 for the Qchannel.

The outputs for the prompt signal pass on to other circuitry used as familiar to those in art for demodulation purposes. The outputs are also fed to estimation means 18, 20 which essentially in this embodiment serve as filters to enhance the signal to noise ratio of the measurement of this position.

Similar operations are performed in the late correlator pair, consisting of multiplier 22 and accumulator 26 for the I channel and multiplier 24 and accumulator 28 for the Qchannel, however the outputs of these are multiplied by the estimates derived from the prompt channel in multipliers 30, 32 and added together in the adder 34.

Similarly, for the early channel similar operations are performed by the multiplier 36 and the accumulator 40, the multiplier 38 and accumulator 42. The output from the accumulators 40,42 are also multiplied by the estimates by the multiples 44, 46, the outputs of which are added by the adder 48.

The outputs of the adders 34, 48 are then subtracted in subtracting means 50. It will be appreciated that these operations can be performed in a different order and in fact two multipliers can be saved if the subtractions are performed prior to the multiplications however, this embodiment better explains the principle.

The output of subtractor means 50 is fed to loop filter means 52 and used to control a clock generator 54 for the sampling of the converters 6, 8 in order to advance or retard the timing of the sampling in such a way to cause the prompt signal to coincide with correlation at the peak of the correlation function. It will be appreciated that additional embodiments of this invention are possible, for example, the sampling may initially take place at a higher rate than one sample per chip and the generation of samples at one sample per chip may be formed through interpolator means and the timings of the samples generated through the interpolator means can be established through setting up the correct interpolator coefficients and the selection of these can also be controlled from the output of the filter means 52. It will also be appreciated that under some circumstances there may be an improvement if the outputs of estimates 18, 20 are so controlled as to normalise them so that they are constant amplitude and that they embody only the phase information of that estimate.

A local code generator 56 controls the multipliers 10, 12, 22, 24, 36, 58 by way of the circuit 38 which generates the early/late/prompt signal.

A further implementation is shown in Figure 3. Referring to Figure 3 the signal generation means 60 is an antenna. A frequency converter 62 feeds the I and Qchannels via analogue to digital converters 64, 66. As before, the multiplier 68 and accumulator 72 together form a correlator and similarly the multiplier 70 and the accumulator 74 form a further correlator.

The outputs from the correlators feed into frequency phase discrimination means 76 which generates a frequency control signal in the manner familiar to those versed in the art which feeds back to the frequency converter 62 to control the phase of the conversion in such a way that the coherent signal is all contained on the I channel. In this way, for the early and the late signals, it becomes unnecessary to correlate on the Qchannel and thus, a single multiplier 78 and single accumulator 80 only is provided which generates the early signal, and similarly for the late signal a multiplier 82 and an accumulator 84 only is provided.

The outputs from the accumulators 80, 84 are subtracted in subtraction means 86, which feeds the loop filter 88 for controlling the clock generator means 90.

A local code generator 92 generates early/late/prompt signals by way of the circuit 94 for controlling the multipliers 68, 70, 78, 82.

It will be readily appreciated by those skilled in the art that alternative arrangements fully within the scope of the invention.

For example, connection to the frequency converters may be made via cables.

Claims

1. Apparatus for code tracking in a direct sequence spread spectrum receiver, comprising means for receiving a signal, means for converting the received signal into an inphase and quadrature signal, analogue to digital converter means per converting for inphase and quadrature signals into digital signals, a first correlator for handling prompt signals, a second correlator for handling late signals, a third correlator for handling early signals, estimation means for obtaining estimates of the output signals from the first correlator, first and second multiplying and adding means for multiplying the estimates with the output signals from the second and third correlators respectively and adding the inphase and quadrature channels together, subtraction means for subtracting the result from said first and second multiplying means, and control means arranged to receive the output signals from said subtracting means and generate control signals for the analogue to digital converter means.

2. Apparatus as claimed in Claim 1, wherein each correlator comprises a multiplier and an accumulator for handling the inphase signals, and a multiplier and accumulator for handling the quadrature signals.

3. Apparatus as claimed in Claim 1 or Claim 2, wherein the control means comprises a loop filter and clock generator.

4. Apparatus as claimed in Claim 2 or Claim 3, wherein the multipliers in each correlator are controlled by a code generator and means for generating early/late/prompt signal codes.

5. Apparatus for code tracking in a direct sequence spread spectrum receiver, comprising means for receiving a signal, converting means for converting the received signal into an inphase and quadrature signal, analogue to digital converter means for converting the inphase and quadrature signals into digital signals, a first correlator for handling prompt signals, a second correlator for handling late signals, a third correlator for handling early signals, a frequency phase discrimination means for receiving the signals from said first correlator and generating a signal for controlling said converting means in a manner such that a coherent signal is contained on one signal phase channel, subtractor means for subtracting the output signals from said second and third correlators, and control means connected to said subtractor means for controlling said analogue to digital converters.

6. Apparatus as claimed in Claim 5, wherein the first correlator comprises a multiplier and accumulator for each signal channel.

7. Apparatus as claimed in Claim 6, wherein, the second and third correlators comprise a multiplier and accumulator for each signal channel.

8. Apparatus as claimed in any of the preceding Claims 5 to 7, wherein the control means comprises a loop filter and clock generator.

9. Apparatus as claimed in Claim 7 or Claim 8, wherein, the multipliers in each correlator are controlled by a code generator and means for generating early/late/prompt signals.

10. Apparatus substantially as herein before described with reference to Figures 1, 2 and 3 of the accompanying drawings.